mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 16:30:00 +00:00
- Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.
- Use XORP* to implement fneg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25857 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
598463fde4
commit
223547ab31
@ -59,7 +59,7 @@ struct X86ATTAsmPrinter : public X86SharedAsmPrinter {
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void printf64mem(const MachineInstr *MI, unsigned OpNo) {
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printMemReference(MI, OpNo);
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}
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void printf80mem(const MachineInstr *MI, unsigned OpNo) {
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void printf128mem(const MachineInstr *MI, unsigned OpNo) {
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printMemReference(MI, OpNo);
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}
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@ -253,7 +253,8 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM) {
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if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N)) {
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AM.BaseType = X86ISelAddressMode::ConstantPoolBase;
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AM.Base.Reg = CurDAG->getTargetConstantPool(CP->get(), MVT::i32);
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AM.Base.Reg = CurDAG->getTargetConstantPool(CP->get(), MVT::i32,
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CP->getAlignment());
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return false;
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}
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}
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@ -17,6 +17,7 @@
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#include "X86ISelLowering.h"
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#include "X86TargetMachine.h"
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#include "llvm/CallingConv.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@ -208,16 +209,20 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
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setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
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// Use ANDPD to simulate FABS.
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setOperationAction(ISD::FABS , MVT::f64, Custom);
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setOperationAction(ISD::FABS , MVT::f32, Custom);
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// Use XORP to simulate FNEG.
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setOperationAction(ISD::FNEG , MVT::f64, Custom);
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setOperationAction(ISD::FNEG , MVT::f32, Custom);
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// We don't support sin/cos/sqrt/fmod
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FABS , MVT::f64, Custom);
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setOperationAction(ISD::FNEG , MVT::f64, Expand);
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setOperationAction(ISD::FREM , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FABS , MVT::f32, Custom);
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setOperationAction(ISD::FNEG , MVT::f32, Expand);
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setOperationAction(ISD::FREM , MVT::f32, Expand);
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// Expand FP immediates into loads from the stack, except for the special
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@ -1567,11 +1572,44 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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}
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case ISD::FABS: {
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MVT::ValueType VT = Op.getValueType();
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SDOperand Mask = (VT == MVT::f64)
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? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), MVT::f64)
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: DAG.getConstantFP(BitsToFloat (~(1U << 31)), MVT::f32);
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const Type *OpNTy = MVT::getTypeForValueType(VT);
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std::vector<Constant*> CV;
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if (VT == MVT::f64) {
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CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63))));
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CV.push_back(ConstantFP::get(OpNTy, 0.0));
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} else {
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CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31))));
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CV.push_back(ConstantFP::get(OpNTy, 0.0));
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CV.push_back(ConstantFP::get(OpNTy, 0.0));
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CV.push_back(ConstantFP::get(OpNTy, 0.0));
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}
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Constant *CS = ConstantStruct::get(CV);
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SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
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SDOperand Mask
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= DAG.getNode(X86ISD::LOAD_PACK,
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VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
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return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
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}
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case ISD::FNEG: {
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MVT::ValueType VT = Op.getValueType();
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const Type *OpNTy = MVT::getTypeForValueType(VT);
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std::vector<Constant*> CV;
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if (VT == MVT::f64) {
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CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63)));
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CV.push_back(ConstantFP::get(OpNTy, 0.0));
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} else {
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CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31)));
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CV.push_back(ConstantFP::get(OpNTy, 0.0));
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CV.push_back(ConstantFP::get(OpNTy, 0.0));
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CV.push_back(ConstantFP::get(OpNTy, 0.0));
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}
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Constant *CS = ConstantStruct::get(CV);
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SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
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SDOperand Mask
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= DAG.getNode(X86ISD::LOAD_PACK,
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VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
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return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
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}
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case ISD::SETCC: {
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assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
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SDOperand Cond;
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@ -1923,6 +1961,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::SHLD: return "X86ISD::SHLD";
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case X86ISD::SHRD: return "X86ISD::SHRD";
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case X86ISD::FAND: return "X86ISD::FAND";
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case X86ISD::FXOR: return "X86ISD::FXOR";
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case X86ISD::FILD: return "X86ISD::FILD";
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case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
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case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
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@ -1942,6 +1981,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
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case X86ISD::REP_STOS: return "X86ISD::RET_STOS";
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case X86ISD::REP_MOVS: return "X86ISD::RET_MOVS";
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case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
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}
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}
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@ -45,6 +45,10 @@ namespace llvm {
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/// to X86::ANDPS or X86::ANDPD.
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FAND,
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/// FXOR - Bitwise logical XOR of floating point values. This corresponds
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/// to X86::XORPS or X86::XORPD.
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FXOR,
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/// FILD - This instruction implements SINT_TO_FP with the integer source
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/// in memory and FP reg result. This corresponds to the X86::FILD*m
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/// instructions. It has three inputs (token chain, address, and source
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@ -137,6 +141,10 @@ namespace llvm {
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/// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
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REP_MOVS,
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/// LOAD_PACK Load a 128-bit packed float / double value. It has the same
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/// operands as a normal load.
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LOAD_PACK,
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};
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// X86 specific condition code. These correspond to X86_*_COND in
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@ -70,6 +70,8 @@ def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
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def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest,
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[SDNPOutFlag]>;
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@ -122,6 +124,9 @@ def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
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def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
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[SDNPHasChain, SDNPOutFlag]>;
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def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
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[SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// X86 Operand Definitions.
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//
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@ -140,7 +145,7 @@ def i32mem : X86MemOperand<"printi32mem">;
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def i64mem : X86MemOperand<"printi64mem">;
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def f32mem : X86MemOperand<"printf32mem">;
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def f64mem : X86MemOperand<"printf64mem">;
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def f80mem : X86MemOperand<"printf80mem">;
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def f128mem : X86MemOperand<"printf128mem">;
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def SSECC : Operand<i8> {
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let PrintMethod = "printSSECC";
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@ -357,6 +362,9 @@ def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>;
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def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extload node:$ptr, i1))>;
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def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extload node:$ptr, f32))>;
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def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
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def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
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//===----------------------------------------------------------------------===//
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// Instruction templates...
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@ -2566,43 +2574,51 @@ def ORPDrr : I<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
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"orpd {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE2]>, TB, OpSize;
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def XORPSrr : I<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
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"xorps {$src2, $dst|$dst, $src2}", []>,
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"xorps {$src2, $dst|$dst, $src2}",
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[(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>,
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Requires<[HasSSE1]>, TB;
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def XORPDrr : I<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
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"xorpd {$src2, $dst|$dst, $src2}", []>,
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"xorpd {$src2, $dst|$dst, $src2}",
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[(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>,
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Requires<[HasSSE2]>, TB, OpSize;
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}
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def ANDPSrm : I<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
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def ANDPSrm : I<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
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"andps {$src2, $dst|$dst, $src2}",
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[]>,
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[(set FR32:$dst, (X86fand FR32:$src1,
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(X86loadpf32 addr:$src2)))]>,
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Requires<[HasSSE1]>, TB;
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def ANDPDrm : I<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
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def ANDPDrm : I<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
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"andpd {$src2, $dst|$dst, $src2}",
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[]>,
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[(set FR64:$dst, (X86fand FR64:$src1,
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(X86loadpf64 addr:$src2)))]>,
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Requires<[HasSSE2]>, TB, OpSize;
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def ORPSrm : I<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
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def ORPSrm : I<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
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"orps {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE1]>, TB;
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def ORPDrm : I<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
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def ORPDrm : I<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
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"orpd {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE2]>, TB, OpSize;
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def XORPSrm : I<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
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"xorps {$src2, $dst|$dst, $src2}", []>,
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def XORPSrm : I<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
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"xorps {$src2, $dst|$dst, $src2}",
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[(set FR32:$dst, (X86fxor FR32:$src1,
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(X86loadpf32 addr:$src2)))]>,
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Requires<[HasSSE1]>, TB;
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def XORPDrm : I<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
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"xorpd {$src2, $dst|$dst, $src2}", []>,
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def XORPDrm : I<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
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"xorpd {$src2, $dst|$dst, $src2}",
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[(set FR64:$dst, (X86fxor FR64:$src1,
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(X86loadpf64 addr:$src2)))]>,
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Requires<[HasSSE2]>, TB, OpSize;
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def ANDNPSrr : I<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
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"andnps {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE1]>, TB;
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def ANDNPSrm : I<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
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def ANDNPSrm : I<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
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"andnps {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE1]>, TB;
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def ANDNPDrr : I<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
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"andnpd {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE2]>, TB, OpSize;
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def ANDNPDrm : I<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
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def ANDNPDrm : I<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
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"andnpd {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE2]>, TB, OpSize;
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@ -2981,6 +2997,42 @@ def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
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(ops i16mem:$dst), "fldcw $dst", []>;
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//===----------------------------------------------------------------------===//
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// XMM Packed Floating point support (requires SSE / SSE2)
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//===----------------------------------------------------------------------===//
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def MOVAPSrr : I<0x28, MRMSrcMem, (ops V4F4:$dst, V4F4:$src),
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"movaps {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, XS;
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def MOVAPDrr : I<0x28, MRMSrcMem, (ops V2F8:$dst, V2F8:$src),
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"movapd {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE2]>, XD;
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def MOVAPSrm : I<0x28, MRMSrcMem, (ops V4F4:$dst, f128mem:$src),
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"movaps {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, XS;
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def MOVAPSmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V4F4:$src),
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"movaps {$src, $dst|$dst, $src}",[]>,
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Requires<[HasSSE1]>, XD;
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def MOVAPDrm : I<0x28, MRMSrcMem, (ops V2F8:$dst, f128mem:$src),
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"movapd {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, XD;
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def MOVAPDmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V2F8:$src),
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"movapd {$src, $dst|$dst, $src}",[]>,
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Requires<[HasSSE2]>, XD;
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// Pseudo-instructions to load FR32 / FR64 from f128mem using movaps / movapd.
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// Upper bits are disregarded.
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def MOVSAPSrm : I<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
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"movaps {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (X86loadpf32 addr:$src))]>,
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Requires<[HasSSE1]>, XS;
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def MOVSAPDrm : I<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
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"movapd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (X86loadpf64 addr:$src))]>,
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Requires<[HasSSE1]>, XD;
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions
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//===----------------------------------------------------------------------===//
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@ -76,8 +76,8 @@ struct X86IntelAsmPrinter : public X86SharedAsmPrinter {
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O << "QWORD PTR ";
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printMemReference(MI, OpNo);
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}
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void printf80mem(const MachineInstr *MI, unsigned OpNo) {
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O << "XWORD PTR ";
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void printf128mem(const MachineInstr *MI, unsigned OpNo) {
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O << "XMMWORD PTR ";
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printMemReference(MI, OpNo);
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}
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