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[FastISel][AArch64] Add {s|u}{add|sub|mul}.with.overflow intrinsic support.
This commit adds support for the {s|u}{add|sub|mul}.with.overflow intrinsics.
The unit tests for FastISel will be enabled in a later commit, once there is
also branch and select folding support.
This is related to <rdar://problem/17831117>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214348 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
07731b34fb
commit
2235d7b9a7
@ -1533,6 +1533,177 @@ bool AArch64FastISel::FastLowerIntrinsicCall(const IntrinsicInst *II) {
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.addImm(1);
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return true;
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}
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case Intrinsic::sadd_with_overflow:
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case Intrinsic::uadd_with_overflow:
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case Intrinsic::ssub_with_overflow:
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case Intrinsic::usub_with_overflow:
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case Intrinsic::smul_with_overflow:
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case Intrinsic::umul_with_overflow: {
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// This implements the basic lowering of the xalu with overflow intrinsics.
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const Function *Callee = II->getCalledFunction();
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auto *Ty = cast<StructType>(Callee->getReturnType());
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Type *RetTy = Ty->getTypeAtIndex(0U);
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Type *CondTy = Ty->getTypeAtIndex(1);
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MVT VT;
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if (!isTypeLegal(RetTy, VT))
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return false;
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if (VT != MVT::i32 && VT != MVT::i64)
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return false;
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const Value *LHS = II->getArgOperand(0);
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const Value *RHS = II->getArgOperand(1);
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// Canonicalize immediate to the RHS.
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if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS) &&
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isCommutativeIntrinsic(II))
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std::swap(LHS, RHS);
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unsigned LHSReg = getRegForValue(LHS);
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if (!LHSReg)
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return false;
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bool LHSIsKill = hasTrivialKill(LHS);
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unsigned RHSReg = 0;
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bool RHSIsKill = false;
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bool UseImm = true;
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if (!isa<ConstantInt>(RHS)) {
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RHSReg = getRegForValue(RHS);
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if (!RHSReg)
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return false;
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RHSIsKill = hasTrivialKill(RHS);
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UseImm = false;
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}
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unsigned Opc = 0;
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unsigned MulReg = 0;
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AArch64CC::CondCode CC = AArch64CC::Invalid;
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bool Is64Bit = VT == MVT::i64;
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switch (II->getIntrinsicID()) {
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default: llvm_unreachable("Unexpected intrinsic!");
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case Intrinsic::sadd_with_overflow:
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if (UseImm)
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Opc = Is64Bit ? AArch64::ADDSXri : AArch64::ADDSWri;
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else
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Opc = Is64Bit ? AArch64::ADDSXrr : AArch64::ADDSWrr;
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CC = AArch64CC::VS;
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break;
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case Intrinsic::uadd_with_overflow:
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if (UseImm)
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Opc = Is64Bit ? AArch64::ADDSXri : AArch64::ADDSWri;
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else
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Opc = Is64Bit ? AArch64::ADDSXrr : AArch64::ADDSWrr;
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CC = AArch64CC::HS;
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break;
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case Intrinsic::ssub_with_overflow:
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if (UseImm)
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Opc = Is64Bit ? AArch64::SUBSXri : AArch64::SUBSWri;
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else
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Opc = Is64Bit ? AArch64::SUBSXrr : AArch64::SUBSWrr;
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CC = AArch64CC::VS;
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break;
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case Intrinsic::usub_with_overflow:
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if (UseImm)
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Opc = Is64Bit ? AArch64::SUBSXri : AArch64::SUBSWri;
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else
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Opc = Is64Bit ? AArch64::SUBSXrr : AArch64::SUBSWrr;
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CC = AArch64CC::LO;
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break;
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case Intrinsic::smul_with_overflow: {
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CC = AArch64CC::NE;
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if (UseImm) {
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RHSReg = getRegForValue(RHS);
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if (!RHSReg)
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return false;
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RHSIsKill = hasTrivialKill(RHS);
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}
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if (VT == MVT::i32) {
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MulReg = Emit_SMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
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unsigned ShiftReg = Emit_LSR_ri(MVT::i64, MulReg, false, 32);
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MulReg = FastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
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AArch64::sub_32);
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ShiftReg = FastEmitInst_extractsubreg(VT, ShiftReg, /*IsKill=*/true,
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AArch64::sub_32);
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unsigned CmpReg = createResultReg(TLI.getRegClassFor(VT));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::SUBSWrs), CmpReg)
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.addReg(ShiftReg, getKillRegState(true))
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.addReg(MulReg, getKillRegState(false))
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.addImm(159); // 159 <-> asr #31
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} else {
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assert(VT == MVT::i64 && "Unexpected value type.");
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MulReg = Emit_MUL_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
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unsigned SMULHReg = FastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,
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RHSReg, RHSIsKill);
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unsigned CmpReg = createResultReg(TLI.getRegClassFor(VT));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::SUBSXrs), CmpReg)
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.addReg(SMULHReg, getKillRegState(true))
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.addReg(MulReg, getKillRegState(false))
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.addImm(191); // 191 <-> asr #63
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}
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break;
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}
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case Intrinsic::umul_with_overflow: {
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CC = AArch64CC::NE;
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if (UseImm) {
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RHSReg = getRegForValue(RHS);
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if (!RHSReg)
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return false;
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RHSIsKill = hasTrivialKill(RHS);
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}
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if (VT == MVT::i32) {
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MulReg = Emit_UMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
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unsigned CmpReg = createResultReg(TLI.getRegClassFor(MVT::i64));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::SUBSXrs), CmpReg)
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.addReg(AArch64::XZR, getKillRegState(true))
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.addReg(MulReg, getKillRegState(false))
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.addImm(96); // 96 <-> lsr #32
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MulReg = FastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
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AArch64::sub_32);
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} else {
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assert(VT == MVT::i64 && "Unexpected value type.");
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MulReg = Emit_MUL_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
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unsigned UMULHReg = FastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,
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RHSReg, RHSIsKill);
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unsigned CmpReg = createResultReg(TLI.getRegClassFor(VT));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::SUBSXrr), CmpReg)
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.addReg(AArch64::XZR, getKillRegState(true))
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.addReg(UMULHReg, getKillRegState(false));
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}
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break;
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}
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}
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
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if (Opc) {
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MachineInstrBuilder MIB;
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
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ResultReg)
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.addReg(LHSReg, getKillRegState(LHSIsKill));
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if (UseImm)
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MIB.addImm(cast<ConstantInt>(RHS)->getZExtValue());
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else
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MIB.addReg(RHSReg, getKillRegState(RHSIsKill));
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}
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else
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(MulReg);
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unsigned ResultReg2 = FuncInfo.CreateRegs(CondTy);
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assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers.");
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
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ResultReg2)
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.addReg(AArch64::WZR, getKillRegState(true))
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.addReg(AArch64::WZR, getKillRegState(true))
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.addImm(getInvertedCondCode(CC));
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UpdateValueMap(II, ResultReg, 2);
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return true;
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}
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}
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return false;
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}
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