mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
Use the generic vector register classes VR64 / VR128 rather than V4F32,
V8I16, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26838 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
4496a50deb
commit
2246f8449f
@ -13,6 +13,39 @@
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// FPStack specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>;
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def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
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def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
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SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
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def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
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SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
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def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisPtrTy<1>,
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SDTCisVT<2, OtherVT>]>;
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def SDTX86FpToIMem: SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
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def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
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[SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
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def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
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[SDNPHasChain, SDNPOutFlag]>;
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def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
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[SDNPHasChain]>;
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def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
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[SDNPHasChain, SDNPInFlag]>;
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def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
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[SDNPHasChain]>;
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def X86fildflag: SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
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[SDNPHasChain, SDNPOutFlag]>;
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def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
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[SDNPHasChain]>;
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def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
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[SDNPHasChain]>;
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def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
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[SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// FPStack pattern fragments
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//===----------------------------------------------------------------------===//
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@ -41,17 +41,6 @@ def SDT_X86CallSeqEnd : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
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def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
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def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>;
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def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
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def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
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SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
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def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
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SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
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def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisPtrTy<1>,
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SDTCisVT<2, OtherVT>]>;
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def SDTX86FpToIMem: SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
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def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
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def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
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@ -61,11 +50,6 @@ def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
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def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
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def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
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def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest,
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[SDNPOutFlag]>;
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def X86test : SDNode<"X86ISD::TEST", SDTX86CmpTest,
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@ -91,26 +75,6 @@ def X86callseq_end :
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def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
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[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
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def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
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[SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
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def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
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[SDNPHasChain, SDNPOutFlag]>;
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def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
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[SDNPHasChain]>;
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def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
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[SDNPHasChain, SDNPInFlag]>;
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def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
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[SDNPHasChain]>;
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def X86fildflag: SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
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[SDNPHasChain, SDNPOutFlag]>;
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def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
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[SDNPHasChain]>;
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def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
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[SDNPHasChain]>;
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def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
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[SDNPHasChain]>;
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def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
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[SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
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def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
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@ -119,9 +83,6 @@ def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
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def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
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[SDNPHasChain, SDNPOutFlag]>;
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def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
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[SDNPHasChain]>;
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def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
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//===----------------------------------------------------------------------===//
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@ -13,6 +13,17 @@
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SSE specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
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[SDNPHasChain]>;
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def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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//===----------------------------------------------------------------------===//
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// SSE pattern fragments
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//===----------------------------------------------------------------------===//
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@ -20,8 +31,8 @@
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def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
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def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
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def X86loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
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def X86loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
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def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
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def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
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//===----------------------------------------------------------------------===//
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// SSE scalar FP Instructions
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@ -331,329 +342,344 @@ def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2)
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//===----------------------------------------------------------------------===//
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// Move Instructions
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def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
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def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"movaps {$src, $dst|$dst, $src}", []>;
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def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
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def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"movaps {$src, $dst|$dst, $src}",
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[(set V4F32:$dst, (X86loadv4f32 addr:$src))]>;
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def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
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[(set VR128:$dst, (loadv4f32 addr:$src))]>;
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def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"movapd {$src, $dst|$dst, $src}", []>;
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def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
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def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"movapd {$src, $dst|$dst, $src}",
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[(set V2F64:$dst, (X86loadv2f64 addr:$src))]>;
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[(set VR128:$dst, (loadv2f64 addr:$src))]>;
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def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, V4F32:$src),
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def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
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"movaps {$src, $dst|$dst, $src}",
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[(store V4F32:$src, addr:$dst)]>;
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def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, V2F64:$src),
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[(store (v4f32 VR128:$src), addr:$dst)]>;
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def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
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"movapd {$src, $dst|$dst, $src}",
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[(store V2F64:$src, addr:$dst)]>;
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[(store (v2f64 VR128:$src), addr:$dst)]>;
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def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
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def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"movups {$src, $dst|$dst, $src}", []>;
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def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
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def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"movups {$src, $dst|$dst, $src}", []>;
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def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, V4F32:$src),
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def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
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"movups {$src, $dst|$dst, $src}", []>;
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def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
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def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"movupd {$src, $dst|$dst, $src}", []>;
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def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
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def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"movupd {$src, $dst|$dst, $src}", []>;
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def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, V2F64:$src),
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def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
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"movupd {$src, $dst|$dst, $src}", []>;
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def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops V4F32:$dst, f64mem:$src),
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def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
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"movlps {$src, $dst|$dst, $src}", []>;
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def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, V4F32:$src),
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def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
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"movlps {$src, $dst|$dst, $src}", []>;
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def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops V2F64:$dst, f64mem:$src),
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def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
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"movlpd {$src, $dst|$dst, $src}", []>;
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def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, V2F64:$src),
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def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
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"movlpd {$src, $dst|$dst, $src}", []>;
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def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops V4F32:$dst, f64mem:$src),
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def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
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"movhps {$src, $dst|$dst, $src}", []>;
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def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, V4F32:$src),
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def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
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"movhps {$src, $dst|$dst, $src}", []>;
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def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops V2F64:$dst, f64mem:$src),
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def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
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"movhpd {$src, $dst|$dst, $src}", []>;
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def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, V2F64:$src),
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def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
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"movhpd {$src, $dst|$dst, $src}", []>;
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def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
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def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"movlhps {$src, $dst|$dst, $src}", []>;
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def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
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def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"movlhps {$src, $dst|$dst, $src}", []>;
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def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, V4F32:$src),
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def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
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"movmskps {$src, $dst|$dst, $src}", []>;
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def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, V2F64:$src),
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def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
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"movmskpd {$src, $dst|$dst, $src}", []>;
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// Conversion instructions
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def CVTPI2PSrr : PSI<0x2A, MRMSrcReg, (ops V4F32:$dst, V2I32:$src),
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def CVTPI2PSrr : PSI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
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"cvtpi2ps {$src, $dst|$dst, $src}", []>;
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def CVTPI2PSrm : PSI<0x2A, MRMSrcMem, (ops V4F32:$dst, i64mem:$src),
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def CVTPI2PSrm : PSI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
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"cvtpi2ps {$src, $dst|$dst, $src}", []>;
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def CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (ops V2F64:$dst, V2I32:$src),
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def CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
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"cvtpi2pd {$src, $dst|$dst, $src}", []>;
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def CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (ops V2F64:$dst, i64mem:$src),
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def CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
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"cvtpi2pd {$src, $dst|$dst, $src}", []>;
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// SSE2 instructions without OpSize prefix
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def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops V4F32:$dst, V4I32:$src),
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def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"cvtdq2ps {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasSSE2]>;
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def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops V4F32:$dst, i128mem:$src),
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def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
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"cvtdq2ps {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasSSE2]>;
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// SSE2 instructions with XS prefix
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def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops V2F64:$dst, V2I32:$src),
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def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR64:$src),
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"cvtdq2pd {$src, $dst|$dst, $src}", []>,
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XS, Requires<[HasSSE2]>;
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def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops V4F32:$dst, i64mem:$src),
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def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
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"cvtdq2pd {$src, $dst|$dst, $src}", []>,
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XS, Requires<[HasSSE2]>;
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def CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (ops V2I32:$dst, V4F32:$src),
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def CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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"cvtps2pi {$src, $dst|$dst, $src}", []>;
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def CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (ops V2I32:$dst, f64mem:$src),
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def CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
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"cvtps2pi {$src, $dst|$dst, $src}", []>;
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def CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (ops V2I32:$dst, V2F64:$src),
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def CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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"cvtpd2pi {$src, $dst|$dst, $src}", []>;
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def CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (ops V2I32:$dst, f128mem:$src),
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def CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
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"cvtpd2pi {$src, $dst|$dst, $src}", []>;
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def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops V4I32:$dst, V4F32:$src),
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def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
|
||||
"cvtps2dq {$src, $dst|$dst, $src}", []>;
|
||||
def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops V4I32:$dst, f128mem:$src),
|
||||
def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
|
||||
"cvtps2dq {$src, $dst|$dst, $src}", []>;
|
||||
// SSE2 packed instructions with XD prefix
|
||||
def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (ops V4I32:$dst, V2F64:$src),
|
||||
def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
|
||||
"cvtpd2dq {$src, $dst|$dst, $src}", []>;
|
||||
def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (ops V4I32:$dst, f128mem:$src),
|
||||
def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
|
||||
"cvtpd2dq {$src, $dst|$dst, $src}", []>;
|
||||
|
||||
// SSE2 instructions without OpSize prefix
|
||||
def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops V4I32:$dst, V2F64:$src),
|
||||
def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
|
||||
"cvtps2pd {$src, $dst|$dst, $src}", []>, TB,
|
||||
Requires<[HasSSE2]>;
|
||||
def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops V4I32:$dst, f64mem:$src),
|
||||
def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
|
||||
"cvtps2pd {$src, $dst|$dst, $src}", []>, TB,
|
||||
Requires<[HasSSE2]>;
|
||||
|
||||
def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops V4F32:$dst, V2F64:$src),
|
||||
def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
|
||||
"cvtpd2ps {$src, $dst|$dst, $src}", []>;
|
||||
def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops V4F32:$dst, f128mem:$src),
|
||||
def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
|
||||
"cvtpd2ps {$src, $dst|$dst, $src}", []>;
|
||||
|
||||
// Arithmetic
|
||||
let isTwoAddress = 1 in {
|
||||
let isCommutable = 1 in {
|
||||
def ADDPSrr : PSI<0x58, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
|
||||
def ADDPSrr : PSI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"addps {$src2, $dst|$dst, $src2}",
|
||||
[(set V4F32:$dst, (fadd V4F32:$src1, V4F32:$src2))]>;
|
||||
def ADDPDrr : PDI<0x58, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
|
||||
[(set VR128:$dst, (v4f32 (fadd VR128:$src1, VR128:$src2)))]>;
|
||||
def ADDPDrr : PDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"addpd {$src2, $dst|$dst, $src2}",
|
||||
[(set V2F64:$dst, (fadd V2F64:$src1, V2F64:$src2))]>;
|
||||
def MULPSrr : PSI<0x59, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
|
||||
[(set VR128:$dst, (v2f64 (fadd VR128:$src1, VR128:$src2)))]>;
|
||||
def MULPSrr : PSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"mulps {$src2, $dst|$dst, $src2}",
|
||||
[(set V4F32:$dst, (fmul V4F32:$src1, V4F32:$src2))]>;
|
||||
def MULPDrr : PDI<0x59, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
|
||||
[(set VR128:$dst, (v4f32 (fmul VR128:$src1, VR128:$src2)))]>;
|
||||
def MULPDrr : PDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"mulpd {$src2, $dst|$dst, $src2}",
|
||||
[(set V2F64:$dst, (fmul V2F64:$src1, V2F64:$src2))]>;
|
||||
[(set VR128:$dst, (v2f64 (fmul VR128:$src1, VR128:$src2)))]>;
|
||||
}
|
||||
|
||||
def ADDPSrm : PSI<0x58, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
|
||||
def ADDPSrm : PSI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"addps {$src2, $dst|$dst, $src2}",
|
||||
[(set V4F32:$dst, (fadd V4F32:$src1,
|
||||
(X86loadv4f32 addr:$src2)))]>;
|
||||
def ADDPDrm : PDI<0x58, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
|
||||
[(set VR128:$dst, (v4f32 (fadd VR128:$src1,
|
||||
(load addr:$src2))))]>;
|
||||
def ADDPDrm : PDI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"addpd {$src2, $dst|$dst, $src2}",
|
||||
[(set V2F64:$dst, (fadd V2F64:$src1,
|
||||
(X86loadv2f64 addr:$src2)))]>;
|
||||
def MULPSrm : PSI<0x59, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
|
||||
[(set VR128:$dst, (v2f64 (fadd VR128:$src1,
|
||||
(load addr:$src2))))]>;
|
||||
def MULPSrm : PSI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"mulps {$src2, $dst|$dst, $src2}",
|
||||
[(set V4F32:$dst, (fmul V4F32:$src1,
|
||||
(X86loadv4f32 addr:$src2)))]>;
|
||||
def MULPDrm : PDI<0x59, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
|
||||
[(set VR128:$dst, (v4f32 (fmul VR128:$src1,
|
||||
(load addr:$src2))))]>;
|
||||
def MULPDrm : PDI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"mulpd {$src2, $dst|$dst, $src2}",
|
||||
[(set V2F64:$dst, (fmul V2F64:$src1,
|
||||
(X86loadv2f64 addr:$src2)))]>;
|
||||
[(set VR128:$dst, (v2f64 (fmul VR128:$src1,
|
||||
(load addr:$src2))))]>;
|
||||
|
||||
def DIVPSrr : PSI<0x5E, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
|
||||
"divps {$src2, $dst|$dst, $src2}",
|
||||
[(set V4F32:$dst, (fdiv V4F32:$src1, V4F32:$src2))]>;
|
||||
def DIVPSrm : PSI<0x5E, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
|
||||
"divps {$src2, $dst|$dst, $src2}",
|
||||
[(set V4F32:$dst, (fdiv V4F32:$src1,
|
||||
(X86loadv4f32 addr:$src2)))]>;
|
||||
def DIVPDrr : PDI<0x5E, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
|
||||
def DIVPSrr : PSI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"divps {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v4f32 (fdiv VR128:$src1, VR128:$src2)))]>;
|
||||
def DIVPSrm : PSI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"divps {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v4f32 (fdiv VR128:$src1,
|
||||
(load addr:$src2))))]>;
|
||||
def DIVPDrr : PDI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"divpd {$src2, $dst|$dst, $src2}",
|
||||
[(set V2F64:$dst, (fdiv V2F64:$src1, V2F64:$src2))]>;
|
||||
def DIVPDrm : PDI<0x5E, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
|
||||
[(set VR128:$dst, (v2f64 (fdiv VR128:$src1, VR128:$src2)))]>;
|
||||
def DIVPDrm : PDI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"divpd {$src2, $dst|$dst, $src2}",
|
||||
[(set V2F64:$dst, (fdiv V2F64:$src1,
|
||||
(X86loadv2f64 addr:$src2)))]>;
|
||||
[(set VR128:$dst, (v2f64 (fdiv VR128:$src1,
|
||||
(load addr:$src2))))]>;
|
||||
|
||||
def SUBPSrr : PSI<0x5C, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
|
||||
"subps {$src2, $dst|$dst, $src2}",
|
||||
[(set V4F32:$dst, (fsub V4F32:$src1, V4F32:$src2))]>;
|
||||
def SUBPSrm : PSI<0x5C, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
|
||||
"subps {$src2, $dst|$dst, $src2}",
|
||||
[(set V4F32:$dst, (fsub V4F32:$src1,
|
||||
(X86loadv4f32 addr:$src2)))]>;
|
||||
def SUBPDrr : PDI<0x5C, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
|
||||
"subpd {$src2, $dst|$dst, $src2}",
|
||||
[(set V2F64:$dst, (fsub V2F64:$src1, V2F64:$src2))]>;
|
||||
def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
|
||||
"subpd {$src2, $dst|$dst, $src2}",
|
||||
[(set V2F64:$dst, (fsub V2F64:$src1,
|
||||
(X86loadv2f64 addr:$src2)))]>;
|
||||
def SUBPSrr : PSI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"subps {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v4f32 (fsub VR128:$src1, VR128:$src2)))]>;
|
||||
def SUBPSrm : PSI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"subps {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v4f32 (fsub VR128:$src1,
|
||||
(load addr:$src2))))]>;
|
||||
def SUBPDrr : PDI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"subpd {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (fsub VR128:$src1, VR128:$src2))]>;
|
||||
def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"subpd {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (fsub VR128:$src1,
|
||||
(load addr:$src2)))]>;
|
||||
}
|
||||
|
||||
def SQRTPSrr : PSI<0x51, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
|
||||
"sqrtps {$src, $dst|$dst, $src}",
|
||||
[(set V4F32:$dst, (fsqrt V4F32:$src))]>;
|
||||
def SQRTPSrm : PSI<0x51, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
|
||||
"sqrtps {$src, $dst|$dst, $src}",
|
||||
[(set V4F32:$dst, (fsqrt (X86loadv4f32 addr:$src)))]>;
|
||||
def SQRTPDrr : PDI<0x51, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
|
||||
"sqrtpd {$src, $dst|$dst, $src}",
|
||||
[(set V2F64:$dst, (fsqrt V2F64:$src))]>;
|
||||
def SQRTPDrm : PDI<0x51, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
|
||||
"sqrtpd {$src, $dst|$dst, $src}",
|
||||
[(set V2F64:$dst, (fsqrt (X86loadv2f64 addr:$src)))]>;
|
||||
def SQRTPSrr : PSI<0x51, MRMSrcReg, (ops VR128:$dst, VR128:$src),
|
||||
"sqrtps {$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (v4f32 (fsqrt VR128:$src)))]>;
|
||||
def SQRTPSrm : PSI<0x51, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
|
||||
"sqrtps {$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (v4f32 (fsqrt (load addr:$src))))]>;
|
||||
def SQRTPDrr : PDI<0x51, MRMSrcReg, (ops VR128:$dst, VR128:$src),
|
||||
"sqrtpd {$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (v2f64 (fsqrt VR128:$src)))]>;
|
||||
def SQRTPDrm : PDI<0x51, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
|
||||
"sqrtpd {$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (v2f64 (fsqrt (load addr:$src))))]>;
|
||||
|
||||
def RSQRTPSrr : PSI<0x52, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
|
||||
"rsqrtps {$src, $dst|$dst, $src}", []>;
|
||||
def RSQRTPSrm : PSI<0x52, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
|
||||
"rsqrtps {$src, $dst|$dst, $src}", []>;
|
||||
def RCPPSrr : PSI<0x53, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
|
||||
def RSQRTPSrr : PSI<0x52, MRMSrcReg, (ops VR128:$dst, VR128:$src),
|
||||
"rsqrtps {$src, $dst|$dst, $src}", []>;
|
||||
def RSQRTPSrm : PSI<0x52, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
|
||||
"rsqrtps {$src, $dst|$dst, $src}", []>;
|
||||
def RCPPSrr : PSI<0x53, MRMSrcReg, (ops VR128:$dst, VR128:$src),
|
||||
"rcpps {$src, $dst|$dst, $src}", []>;
|
||||
def RCPPSrm : PSI<0x53, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
|
||||
def RCPPSrm : PSI<0x53, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
|
||||
"rcpps {$src, $dst|$dst, $src}", []>;
|
||||
|
||||
def MAXPSrr : PSI<0x5F, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
|
||||
def MAXPSrr : PSI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
|
||||
"maxps {$src, $dst|$dst, $src}", []>;
|
||||
def MAXPSrm : PSI<0x5F, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
|
||||
def MAXPSrm : PSI<0x5F, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
|
||||
"maxps {$src, $dst|$dst, $src}", []>;
|
||||
def MAXPDrr : PDI<0x5F, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
|
||||
def MAXPDrr : PDI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
|
||||
"maxpd {$src, $dst|$dst, $src}", []>;
|
||||
def MAXPDrm : PDI<0x5F, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
|
||||
def MAXPDrm : PDI<0x5F, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
|
||||
"maxpd {$src, $dst|$dst, $src}", []>;
|
||||
def MINPSrr : PSI<0x5D, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
|
||||
def MINPSrr : PSI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src),
|
||||
"minps {$src, $dst|$dst, $src}", []>;
|
||||
def MINPSrm : PSI<0x5D, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
|
||||
def MINPSrm : PSI<0x5D, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
|
||||
"minps {$src, $dst|$dst, $src}", []>;
|
||||
def MINPDrr : PDI<0x5D, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
|
||||
def MINPDrr : PDI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src),
|
||||
"minpd {$src, $dst|$dst, $src}", []>;
|
||||
def MINPDrm : PDI<0x5D, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
|
||||
def MINPDrm : PDI<0x5D, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
|
||||
"minpd {$src, $dst|$dst, $src}", []>;
|
||||
|
||||
// Logical
|
||||
let isTwoAddress = 1 in {
|
||||
let isCommutable = 1 in {
|
||||
def ANDPSrr : PSI<0x54, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
|
||||
"andps {$src2, $dst|$dst, $src2}",
|
||||
[(set V4F32:$dst, (X86fand V4F32:$src1, V4F32:$src2))]>;
|
||||
def ANDPDrr : PDI<0x54, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
|
||||
def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"andps {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v4i32 (and VR128:$src1, VR128:$src2)))]>;
|
||||
def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"andpd {$src2, $dst|$dst, $src2}",
|
||||
[(set V2F64:$dst, (X86fand V2F64:$src1, V2F64:$src2))]>;
|
||||
def ORPSrr : PSI<0x56, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
|
||||
"orps {$src2, $dst|$dst, $src2}", []>;
|
||||
def ORPDrr : PDI<0x56, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
|
||||
"orpd {$src2, $dst|$dst, $src2}", []>;
|
||||
def XORPSrr : PSI<0x57, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
|
||||
"xorps {$src2, $dst|$dst, $src2}",
|
||||
[(set V4F32:$dst, (X86fxor V4F32:$src1, V4F32:$src2))]>;
|
||||
def XORPDrr : PDI<0x57, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
|
||||
"xorpd {$src2, $dst|$dst, $src2}",
|
||||
[(set V2F64:$dst, (X86fxor V2F64:$src1, V2F64:$src2))]>;
|
||||
[(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
|
||||
def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"orps {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v4i32 (or VR128:$src1, VR128:$src2)))]>;
|
||||
def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"orpd {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
|
||||
def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"xorps {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v4i32 (xor VR128:$src1, VR128:$src2)))]>;
|
||||
def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"xorpd {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
|
||||
}
|
||||
def ANDPSrm : PSI<0x54, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
|
||||
"andps {$src2, $dst|$dst, $src2}",
|
||||
[(set V4F32:$dst, (X86fand V4F32:$src1,
|
||||
(X86loadv4f32 addr:$src2)))]>;
|
||||
def ANDPDrm : PDI<0x54, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
|
||||
"andpd {$src2, $dst|$dst, $src2}",
|
||||
[(set V2F64:$dst, (X86fand V2F64:$src1,
|
||||
(X86loadv2f64 addr:$src2)))]>;
|
||||
def ORPSrm : PSI<0x56, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
|
||||
"orps {$src2, $dst|$dst, $src2}", []>;
|
||||
def ORPDrm : PDI<0x56, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
|
||||
"orpd {$src2, $dst|$dst, $src2}", []>;
|
||||
def XORPSrm : PSI<0x57, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
|
||||
"xorps {$src2, $dst|$dst, $src2}",
|
||||
[(set V4F32:$dst, (X86fxor V4F32:$src1,
|
||||
(X86loadv4f32 addr:$src2)))]>;
|
||||
def XORPDrm : PDI<0x57, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
|
||||
"xorpd {$src2, $dst|$dst, $src2}",
|
||||
[(set V2F64:$dst, (X86fxor V2F64:$src1,
|
||||
(X86loadv2f64 addr:$src2)))]>;
|
||||
def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
|
||||
"andnps {$src2, $dst|$dst, $src2}", []>;
|
||||
def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
|
||||
"andnps {$src2, $dst|$dst, $src2}", []>;
|
||||
def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
|
||||
"andnpd {$src2, $dst|$dst, $src2}", []>;
|
||||
def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
|
||||
"andnpd {$src2, $dst|$dst, $src2}", []>;
|
||||
def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"andps {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v4i32 (and VR128:$src1,
|
||||
(load addr:$src2))))]>;
|
||||
def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"andpd {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v2i64 (and VR128:$src1,
|
||||
(load addr:$src2))))]>;
|
||||
def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"orps {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v4i32 (or VR128:$src1,
|
||||
(load addr:$src2))))]>;
|
||||
def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"orpd {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v2i64 (or VR128:$src1,
|
||||
(load addr:$src2))))]>;
|
||||
def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"xorps {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v4i32 (xor VR128:$src1,
|
||||
(load addr:$src2))))]>;
|
||||
def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"xorpd {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v2i64 (xor VR128:$src1,
|
||||
(load addr:$src2))))]>;
|
||||
def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"andnps {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v4i32 (and (not VR128:$src1),
|
||||
VR128:$src2)))]>;
|
||||
def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"andnps {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v4i32 (and (not VR128:$src1),
|
||||
(load addr:$src2))))]>;
|
||||
def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"andnpd {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v2i64 (and (not VR128:$src1),
|
||||
VR128:$src2)))]>;
|
||||
|
||||
def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"andnpd {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v2i64 (and VR128:$src1,
|
||||
(load addr:$src2))))]>;
|
||||
}
|
||||
|
||||
let isTwoAddress = 1 in {
|
||||
def CMPPSrr : PSI<0xC2, MRMSrcReg,
|
||||
(ops V4F32:$dst, V4F32:$src1, V4F32:$src, SSECC:$cc),
|
||||
(ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
|
||||
"cmp${cc}ps {$src, $dst|$dst, $src}", []>;
|
||||
def CMPPSrm : PSI<0xC2, MRMSrcMem,
|
||||
(ops V4F32:$dst, V4F32:$src1, f128mem:$src, SSECC:$cc),
|
||||
(ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
|
||||
"cmp${cc}ps {$src, $dst|$dst, $src}", []>;
|
||||
def CMPPDrr : PDI<0xC2, MRMSrcReg,
|
||||
(ops V2F64:$dst, V2F64:$src1, V2F64:$src, SSECC:$cc),
|
||||
(ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
|
||||
"cmp${cc}pd {$src, $dst|$dst, $src}", []>;
|
||||
def CMPPDrm : PDI<0xC2, MRMSrcMem,
|
||||
(ops V2F64:$dst, V2F64:$src1, f128mem:$src, SSECC:$cc),
|
||||
(ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
|
||||
"cmp${cc}pd {$src, $dst|$dst, $src}", []>;
|
||||
}
|
||||
|
||||
// Shuffle and unpack instructions
|
||||
def SHUFPSrr : PSI<0xC6, MRMSrcReg,
|
||||
(ops V4F32:$dst, V4F32:$src1, V4F32:$src2, i8imm:$src3),
|
||||
(ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
|
||||
"shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
|
||||
def SHUFPSrm : PSI<0xC6, MRMSrcMem,
|
||||
(ops V4F32:$dst, V4F32:$src1, f128mem:$src2, i8imm:$src3),
|
||||
(ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
|
||||
"shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
|
||||
def SHUFPDrr : PDI<0xC6, MRMSrcReg,
|
||||
(ops V2F64:$dst, V2F64:$src1, V2F64:$src2, i8imm:$src3),
|
||||
(ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
|
||||
"shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
|
||||
def SHUFPDrm : PDI<0xC6, MRMSrcMem,
|
||||
(ops V2F64:$dst, V2F64:$src1, f128mem:$src2, i8imm:$src3),
|
||||
(ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
|
||||
"shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
|
||||
|
||||
def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
|
||||
(ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
|
||||
(ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"unpckhps {$src2, $dst|$dst, $src2}", []>;
|
||||
def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
|
||||
(ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
|
||||
(ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"unpckhps {$src2, $dst|$dst, $src2}", []>;
|
||||
def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
|
||||
(ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
|
||||
(ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"unpckhpd {$src2, $dst|$dst, $src2}", []>;
|
||||
def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
|
||||
(ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
|
||||
(ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"unpckhpd {$src2, $dst|$dst, $src2}", []>;
|
||||
def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
|
||||
(ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
|
||||
(ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"unpcklps {$src2, $dst|$dst, $src2}", []>;
|
||||
def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
|
||||
(ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
|
||||
(ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"unpcklps {$src2, $dst|$dst, $src2}", []>;
|
||||
def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
|
||||
(ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
|
||||
(ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"unpcklpd {$src2, $dst|$dst, $src2}", []>;
|
||||
def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
|
||||
(ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
|
||||
(ops VR128:$dst, VR128:$src1, f128mem:$src2),
|
||||
"unpcklpd {$src2, $dst|$dst, $src2}", []>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -61,9 +61,7 @@ void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
Opc = X86::MOVSSmr;
|
||||
} else if (RC == &X86::FR64RegClass) {
|
||||
Opc = X86::MOVSDmr;
|
||||
} else if (RC == &X86::V4F32RegClass) {
|
||||
Opc = X86::MOVAPSmr;
|
||||
} else if (RC == &X86::V2F64RegClass) {
|
||||
} else if (RC == &X86::VR128RegClass) {
|
||||
Opc = X86::MOVAPDmr;
|
||||
} else {
|
||||
assert(0 && "Unknown regclass");
|
||||
@ -89,9 +87,7 @@ void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
Opc = X86::MOVSSrm;
|
||||
} else if (RC == &X86::FR64RegClass) {
|
||||
Opc = X86::MOVSDrm;
|
||||
} else if (RC == &X86::V4F32RegClass) {
|
||||
Opc = X86::MOVAPSrm;
|
||||
} else if (RC == &X86::V2F64RegClass) {
|
||||
} else if (RC == &X86::VR128RegClass) {
|
||||
Opc = X86::MOVAPDrm;
|
||||
} else {
|
||||
assert(0 && "Unknown regclass");
|
||||
@ -117,9 +113,7 @@ void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||
Opc = X86::FsMOVAPSrr;
|
||||
} else if (RC == &X86::FR64RegClass) {
|
||||
Opc = X86::FsMOVAPDrr;
|
||||
} else if (RC == &X86::V4F32RegClass) {
|
||||
Opc = X86::MOVAPSrr;
|
||||
} else if (RC == &X86::V2F64RegClass) {
|
||||
} else if (RC == &X86::VR128RegClass) {
|
||||
Opc = X86::MOVAPDrr;
|
||||
} else {
|
||||
assert(0 && "Unknown regclass");
|
||||
|
||||
Loading…
Reference in New Issue
Block a user