mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
This is a simple patch that changes RRX and RRXS to accept all registers as operands.
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
7e129466d8
commit
2248cf5906
@ -5233,7 +5233,7 @@ def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
|
|||||||
cc_out:$s)>;
|
cc_out:$s)>;
|
||||||
}
|
}
|
||||||
def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
|
def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
|
||||||
(ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
|
(ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
|
||||||
let TwoOperandAliasConstraint = "$Rn = $Rd" in {
|
let TwoOperandAliasConstraint = "$Rn = $Rd" in {
|
||||||
def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
|
def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
|
||||||
(ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
|
(ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
|
||||||
|
@ -1645,6 +1645,30 @@ Lforward:
|
|||||||
@ CHECK: rsc r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0xe6,0xe0]
|
@ CHECK: rsc r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0xe6,0xe0]
|
||||||
|
|
||||||
@------------------------------------------------------------------------------
|
@------------------------------------------------------------------------------
|
||||||
|
@ RRX/RRXS
|
||||||
|
@------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
rrx r0, r1
|
||||||
|
rrx sp, pc
|
||||||
|
rrx pc, lr
|
||||||
|
rrx lr, sp
|
||||||
|
|
||||||
|
@ CHECK: rrx r0, r1 @ encoding: [0x61,0x00,0xa0,0xe1]
|
||||||
|
@ CHECK: rrx sp, pc @ encoding: [0x6f,0xd0,0xa0,0xe1]
|
||||||
|
@ CHECK: rrx pc, lr @ encoding: [0x6e,0xf0,0xa0,0xe1]
|
||||||
|
@ CHECK: rrx lr, sp @ encoding: [0x6d,0xe0,0xa0,0xe1]
|
||||||
|
|
||||||
|
rrxs r0, r1
|
||||||
|
rrxs sp, pc
|
||||||
|
rrxs pc, lr
|
||||||
|
rrxs lr, sp
|
||||||
|
|
||||||
|
@CHECK: rrxs r0, r1 @ encoding: [0x61,0x00,0xb0,0xe1]
|
||||||
|
@CHECK: rrxs sp, pc @ encoding: [0x6f,0xd0,0xb0,0xe1]
|
||||||
|
@CHECK: rrxs pc, lr @ encoding: [0x6e,0xf0,0xb0,0xe1]
|
||||||
|
@CHECK: rrxs lr, sp @ encoding: [0x6d,0xe0,0xb0,0xe1]
|
||||||
|
|
||||||
|
@ ------------------------------------------------------------------------------
|
||||||
@ SADD16/SADD8
|
@ SADD16/SADD8
|
||||||
@------------------------------------------------------------------------------
|
@------------------------------------------------------------------------------
|
||||||
sadd16 r1, r2, r3
|
sadd16 r1, r2, r3
|
||||||
|
@ -1300,6 +1300,29 @@
|
|||||||
0x57 0x69 0xe6 0xe0
|
0x57 0x69 0xe6 0xe0
|
||||||
0x77 0x69 0xe6 0xe0
|
0x77 0x69 0xe6 0xe0
|
||||||
|
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
# RRX/RRXS
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
# CHECK: rrx r0, r1
|
||||||
|
# CHECK: rrx sp, pc
|
||||||
|
# CHECK: rrx pc, lr
|
||||||
|
# CHECK: rrx lr, sp
|
||||||
|
|
||||||
|
0x61 0x00 0xa0 0xe1
|
||||||
|
0x6f 0xd0 0xa0 0xe1
|
||||||
|
0x6e 0xf0 0xa0 0xe1
|
||||||
|
0x6d 0xe0 0xa0 0xe1
|
||||||
|
|
||||||
|
# CHECK: rrxs r0, r1
|
||||||
|
# CHECK: rrxs sp, pc
|
||||||
|
# CHECK: rrxs pc, lr
|
||||||
|
# CHECK: rrxs lr, sp
|
||||||
|
|
||||||
|
0x61 0x00 0xb0 0xe1
|
||||||
|
0x6f 0xd0 0xb0 0xe1
|
||||||
|
0x6e 0xf0 0xb0 0xe1
|
||||||
|
0x6d 0xe0 0xb0 0xe1
|
||||||
|
|
||||||
#------------------------------------------------------------------------------
|
#------------------------------------------------------------------------------
|
||||||
# SADD16/SADD8
|
# SADD16/SADD8
|
||||||
#------------------------------------------------------------------------------
|
#------------------------------------------------------------------------------
|
||||||
|
Loading…
Reference in New Issue
Block a user