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R600/SI: Custom-select 32-bit S_BFE from bitwise opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233078 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -121,6 +121,11 @@ private:
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SDNode *SelectADD_SUB_I64(SDNode *N);
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SDNode *SelectDIV_SCALE(SDNode *N);
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SDNode *getS_BFE(unsigned Opcode, SDLoc DL, SDValue Val,
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uint32_t Offset, uint32_t Width);
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SDNode *SelectS_BFEFromShifts(SDNode *N);
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SDNode *SelectS_BFE(SDNode *N);
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// Include the pieces autogenerated from the target description.
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#include "AMDGPUGenDAGISel.inc"
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};
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@ -520,21 +525,11 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
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bool Signed = Opc == AMDGPUISD::BFE_I32;
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// Transformation function, pack the offset and width of a BFE into
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// the format expected by the S_BFE_I32 / S_BFE_U32. In the second
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// source, bits [5:0] contain the offset and bits [22:16] the width.
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uint32_t OffsetVal = Offset->getZExtValue();
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uint32_t WidthVal = Width->getZExtValue();
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uint32_t PackedVal = OffsetVal | WidthVal << 16;
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SDValue PackedOffsetWidth = CurDAG->getTargetConstant(PackedVal, MVT::i32);
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return CurDAG->getMachineNode(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32,
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SDLoc(N),
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MVT::i32,
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N->getOperand(0),
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PackedOffsetWidth);
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return getS_BFE(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32, SDLoc(N),
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N->getOperand(0), OffsetVal, WidthVal);
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}
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case AMDGPUISD::DIV_SCALE: {
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@ -548,6 +543,14 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
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}
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case ISD::ADDRSPACECAST:
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return SelectAddrSpaceCast(N);
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case ISD::AND:
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case ISD::SRL:
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case ISD::SRA:
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if (N->getValueType(0) != MVT::i32 ||
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Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
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break;
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return SelectS_BFE(N);
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}
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return SelectCode(N);
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@ -1150,6 +1153,95 @@ SDNode *AMDGPUDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
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return CurDAG->getNode(ISD::BITCAST, DL, DestVT, Src).getNode();
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}
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SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, SDLoc DL, SDValue Val,
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uint32_t Offset, uint32_t Width) {
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// Transformation function, pack the offset and width of a BFE into
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// the format expected by the S_BFE_I32 / S_BFE_U32. In the second
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// source, bits [5:0] contain the offset and bits [22:16] the width.
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uint32_t PackedVal = Offset | (Width << 16);
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SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, MVT::i32);
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return CurDAG->getMachineNode(Opcode, DL, MVT::i32, Val, PackedConst);
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}
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SDNode *AMDGPUDAGToDAGISel::SelectS_BFEFromShifts(SDNode *N) {
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// "(a << b) srl c)" ---> "BFE_U32 a, (c-b), (32-c)
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// "(a << b) sra c)" ---> "BFE_I32 a, (c-b), (32-c)
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// Predicate: 0 < b <= c < 32
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const SDValue &Shl = N->getOperand(0);
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ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1));
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
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if (B && C) {
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uint32_t BVal = B->getZExtValue();
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uint32_t CVal = C->getZExtValue();
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if (0 < BVal && BVal <= CVal && CVal < 32) {
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bool Signed = N->getOpcode() == ISD::SRA;
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unsigned Opcode = Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32;
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return getS_BFE(Opcode, SDLoc(N), Shl.getOperand(0),
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CVal - BVal, 32 - CVal);
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}
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}
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return SelectCode(N);
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}
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SDNode *AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) {
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switch (N->getOpcode()) {
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case ISD::AND:
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if (N->getOperand(0).getOpcode() == ISD::SRL) {
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// "(a srl b) & mask" ---> "BFE_U32 a, b, popcount(mask)"
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// Predicate: isMask(mask)
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const SDValue &Srl = N->getOperand(0);
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ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1));
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ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
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if (Shift && Mask) {
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uint32_t ShiftVal = Shift->getZExtValue();
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uint32_t MaskVal = Mask->getZExtValue();
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if (isMask_32(MaskVal)) {
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uint32_t WidthVal = countPopulation(MaskVal);
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return getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N), Srl.getOperand(0),
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ShiftVal, WidthVal);
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}
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}
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}
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break;
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case ISD::SRL:
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if (N->getOperand(0).getOpcode() == ISD::AND) {
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// "(a & mask) srl b)" ---> "BFE_U32 a, b, popcount(mask >> b)"
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// Predicate: isMask(mask >> b)
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const SDValue &And = N->getOperand(0);
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ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N->getOperand(1));
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ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(And->getOperand(1));
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if (Shift && Mask) {
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uint32_t ShiftVal = Shift->getZExtValue();
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uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal;
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if (isMask_32(MaskVal)) {
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uint32_t WidthVal = countPopulation(MaskVal);
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return getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N), And.getOperand(0),
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ShiftVal, WidthVal);
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}
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}
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} else if (N->getOperand(0).getOpcode() == ISD::SHL)
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return SelectS_BFEFromShifts(N);
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break;
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case ISD::SRA:
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if (N->getOperand(0).getOpcode() == ISD::SHL)
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return SelectS_BFEFromShifts(N);
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break;
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}
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return SelectCode(N);
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}
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bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
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SDValue &SrcMods) const {
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@ -96,7 +96,6 @@ define void @bfe_i32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw
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ret void
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}
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; FIXME: The shifts should be 1 BFE
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; FUNC-LABEL: {{^}}bfe_i32_test_8:
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; SI: buffer_load_dword
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; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1
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@ -407,16 +406,12 @@ define void @bfe_i32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind {
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ret void
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}
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; XXX - This should really be a single BFE, but the sext_inreg of the
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; extended type i24 is never custom lowered.
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; FUNC-LABEL: {{^}}bfe_sext_in_reg_i24:
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; SI: buffer_load_dword [[LOAD:v[0-9]+]],
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; SI: v_lshlrev_b32_e32 {{v[0-9]+}}, 8, {{v[0-9]+}}
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; SI: v_ashrrev_i32_e32 {{v[0-9]+}}, 8, {{v[0-9]+}}
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; XSI: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 0, 8
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; XSI-NOT: SHL
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; XSI-NOT: SHR
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; XSI: buffer_store_dword [[BFE]],
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; SI-NOT: v_lshl
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; SI-NOT: v_ashr
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; SI: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 0, 24
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; SI: buffer_store_dword [[BFE]],
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define void @bfe_sext_in_reg_i24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32, i32 addrspace(1)* %in, align 4
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 0, i32 24)
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@ -439,7 +439,7 @@ define void @bfe_u32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind {
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; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
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; SI: buffer_store_dword [[VREG]],
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; SI: s_endpgm
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; EG-NOT: BFEfppppppppppppp
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; EG-NOT: BFE
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define void @bfe_u32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind {
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%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 65536, i32 16, i32 8) nounwind readnone
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store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
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@ -575,3 +575,43 @@ define void @simplify_bfe_u32_multi_use_arg(i32 addrspace(1)* %out0,
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store i32 %and, i32 addrspace(1)* %out1, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}lshr_and:
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; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x30006
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; SI: buffer_store_dword
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define void @lshr_and(i32 addrspace(1)* %out, i32 %a) nounwind {
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%b = lshr i32 %a, 6
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%c = and i32 %b, 7
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store i32 %c, i32 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}and_lshr:
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; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x30006
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; SI: buffer_store_dword
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define void @and_lshr(i32 addrspace(1)* %out, i32 %a) nounwind {
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%b = and i32 %a, 448
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%c = lshr i32 %b, 6
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store i32 %c, i32 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}and_lshr2:
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; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x30006
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; SI: buffer_store_dword
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define void @and_lshr2(i32 addrspace(1)* %out, i32 %a) nounwind {
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%b = and i32 %a, 511
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%c = lshr i32 %b, 6
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store i32 %c, i32 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}shl_lshr:
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; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x150002
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; SI: buffer_store_dword
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define void @shl_lshr(i32 addrspace(1)* %out, i32 %a) nounwind {
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%b = shl i32 %a, 9
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%c = lshr i32 %b, 11
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store i32 %c, i32 addrspace(1)* %out, align 8
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ret void
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}
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@ -263,9 +263,9 @@ define void @v_sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)*
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}
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; FUNC-LABEL: {{^}}sext_in_reg_i1_in_i32_other_amount:
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; SI-NOT: {{[^@]}}bfe
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; SI: s_lshl_b32 [[REG:s[0-9]+]], {{s[0-9]+}}, 6
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; SI: s_ashr_i32 {{s[0-9]+}}, [[REG]], 7
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; SI-NOT: s_lshl
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; SI-NOT: s_ashr
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; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
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; EG-NOT: BFE
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@ -282,10 +282,10 @@ define void @sext_in_reg_i1_in_i32_other_amount(i32 addrspace(1)* %out, i32 %a,
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}
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; FUNC-LABEL: {{^}}sext_in_reg_v2i1_in_v2i32_other_amount:
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; SI-DAG: s_lshl_b32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6
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; SI-DAG: s_ashr_i32 {{s[0-9]+}}, [[REG0]], 7
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; SI-DAG: s_lshl_b32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6
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; SI-DAG: s_ashr_i32 {{s[0-9]+}}, [[REG1]], 7
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; SI-NOT: s_lshl
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; SI-NOT: s_ashr
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; SI-DAG: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001
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; SI-DAG: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001
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; SI: s_endpgm
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
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@ -599,8 +599,9 @@ define void @sext_in_reg_i1_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1
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; FUNC-LABEL: {{^}}sext_in_reg_i2_bfe_offset_1:
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; SI: buffer_load_dword
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; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 30, v{{[0-9]+}}
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; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 30, v{{[0-9]+}}
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; SI-NOT: v_lshl
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; SI-NOT: v_ashr
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; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 2
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; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 2
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; SI: s_endpgm
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define void @sext_in_reg_i2_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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