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expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31014 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-10-17 21:05:33 +00:00
parent 04d88ffdb5
commit 226f8bc38c
2 changed files with 33 additions and 0 deletions
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4
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -75,6 +75,10 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SDIV, MVT::i32, Expand);
setOperationAction(ISD::UDIV, MVT::i32, Expand);
setOperationAction(ISD::SREM, MVT::i32, Expand);
setOperationAction(ISD::UREM, MVT::i32, Expand);
setOperationAction(ISD::VASTART, MVT::Other, Custom); setOperationAction(ISD::VASTART, MVT::Other, Custom);
setOperationAction(ISD::VAEND, MVT::Other, Expand); setOperationAction(ISD::VAEND, MVT::Other, Expand);

29
test/CodeGen/ARM/div.ll Normal file
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@ -0,0 +1,29 @@
; RUN: llvm-as < %s | llc -march=arm &&
; RUN: llvm-as < %s | llc -march=arm | grep __divsi3 &&
; RUN: llvm-as < %s | llc -march=arm | grep __udivsi3 &&
; RUN: llvm-as < %s | llc -march=arm | grep __modsi3 &&
; RUN: llvm-as < %s | llc -march=arm | grep __umodsi3
int %f1(int %a, int %b) {
entry:
%tmp1 = div int %a, %b
ret int %tmp1
}
uint %f2(uint %a, uint %b) {
entry:
%tmp1 = div uint %a, %b
ret uint %tmp1
}
int %f3(int %a, int %b) {
entry:
%tmp1 = rem int %a, %b
ret int %tmp1
}
uint %f4(uint %a, uint %b) {
entry:
%tmp1 = rem uint %a, %b
ret uint %tmp1
}