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Rearrange code for selecting vld2 intrinsics. No functionality change.

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This is just to be more consistent with the forthcoming code for vld3/4.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83470 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2009-10-07 17:23:09 +00:00
parent 967f87578d
commit 228c08b8dd
1 changed files with 14 additions and 9 deletions
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23
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -1350,13 +1350,22 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDValue MemAddr, MemUpdate, MemOpc;
if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
return NULL;
EVT RegVT = VT;
if (VT.is64BitVector()) {
switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled vld2 type");
case MVT::v8i8: Opc = ARM::VLD2d8; break;
case MVT::v4i16: Opc = ARM::VLD2d16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD2d32; break;
}
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 4);
}
// Quad registers are loaded as pairs of double registers.
EVT RegVT;
switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled vld2 type");
case MVT::v8i8: Opc = ARM::VLD2d8; break;
case MVT::v4i16: Opc = ARM::VLD2d16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD2d32; break;
case MVT::v16i8: Opc = ARM::VLD2q8; RegVT = MVT::v8i8; break;
case MVT::v8i16: Opc = ARM::VLD2q16; RegVT = MVT::v4i16; break;
case MVT::v4f32: Opc = ARM::VLD2q32; RegVT = MVT::v2f32; break;
@ -1364,10 +1373,6 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
}
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
if (RegVT == VT)
return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 4);
// Quad registers are loaded as pairs of double registers.
std::vector<EVT> ResTys(4, RegVT);
ResTys.push_back(MVT::Other);
SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4);