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Fix PR8811 by teaching MachineVerifier about optional defs.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122199 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich 2010-12-19 21:37:23 +00:00
parent c44270dd6f
commit 22d67cf6ac
1 changed files with 3 additions and 3 deletions
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6
lib/CodeGen/MachineVerifier.cpp
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@ -555,6 +555,7 @@ void
MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
const MachineInstr *MI = MO->getParent();
const TargetInstrDesc &TI = MI->getDesc();
const TargetOperandInfo &TOI = TI.OpInfo[MONum];
// The first TI.NumDefs operands must be explicit register defines
if (MONum < TI.getNumDefs()) {
@ -568,8 +569,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
// Don't check if it's the last operand in a variadic instruction. See,
// e.g., LDM_RET in the arm back end.
if (MO->isReg() && !(TI.isVariadic() && MONum == TI.getNumOperands()-1)) {
if (MO->isDef())
report("Explicit operand marked as def", MO, MONum);
if (MO->isDef() && !TOI.isOptionalDef())
report("Explicit operand marked as def", MO, MONum);
if (MO->isImplicit())
report("Explicit operand marked as implicit", MO, MONum);
}
@ -706,7 +707,6 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
// Check register classes.
if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
const TargetOperandInfo &TOI = TI.OpInfo[MONum];
unsigned SubIdx = MO->getSubReg();
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {