mirror of
https://github.com/c64scene-ar/llvm-6502.git
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[Hexagon] Adding encodings for v5 floating point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225372 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
22efbc70a7
commit
22ddfae848
@ -112,6 +112,332 @@ def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
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let Inst{20-16} = Rss;
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}
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let Uses = [USR], isFP = 1, hasNewValue = 1, opNewValue = 0 in
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class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp>
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: MInst<(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, IntRegs:$Rt),
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"$Rd = "#mnemonic#"($Rs, $Rt)", [],
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"" , M_tc_3or4x_SLOT23 > ,
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Requires<[HasV5T]> {
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bits<5> Rd;
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bits<5> Rs;
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bits<5> Rt;
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let IClass = 0b1110;
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let Inst{27-24} = 0b1011;
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let Inst{23-21} = MajOp;
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let Inst{20-16} = Rs;
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let Inst{13} = 0b0;
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let Inst{12-8} = Rt;
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let Inst{7-5} = MinOp;
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let Inst{4-0} = Rd;
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}
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let isCommutable = 1, isCodeGenOnly = 0 in {
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def F2_sfadd : T_MInstFloat < "sfadd", 0b000, 0b000>;
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def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>;
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}
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let isCodeGenOnly = 0 in
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def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>;
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let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
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def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
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def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>;
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}
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let isCodeGenOnly = 0 in {
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def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>;
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def F2_sffixupd : T_MInstFloat < "sffixupd", 0b110, 0b001>;
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}
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// F2_sfrecipa: Reciprocal approximation for division.
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let Uses = [USR], isPredicateLate = 1, isFP = 1,
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hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
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def F2_sfrecipa: MInst <
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(outs IntRegs:$Rd, PredRegs:$Pe),
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(ins IntRegs:$Rs, IntRegs:$Rt),
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"$Rd, $Pe = sfrecipa($Rs, $Rt)">,
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Requires<[HasV5T]> {
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bits<5> Rd;
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bits<2> Pe;
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bits<5> Rs;
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bits<5> Rt;
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let IClass = 0b1110;
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let Inst{27-21} = 0b1011111;
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let Inst{20-16} = Rs;
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let Inst{13} = 0b0;
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let Inst{12-8} = Rt;
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let Inst{7} = 0b1;
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let Inst{6-5} = Pe;
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let Inst{4-0} = Rd;
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}
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// F2_dfcmpeq: Floating point compare for equal.
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let Uses = [USR], isCompare = 1, isFP = 1 in
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class T_fcmp <string mnemonic, RegisterClass RC, bits<3> MinOp,
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list<dag> pattern = [] >
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: ALU64Inst <(outs PredRegs:$dst), (ins RC:$src1, RC:$src2),
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"$dst = "#mnemonic#"($src1, $src2)", pattern,
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"" , ALU64_tc_2early_SLOT23 > ,
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Requires<[HasV5T]> {
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bits<2> dst;
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bits<5> src1;
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bits<5> src2;
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let IClass = 0b1101;
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let Inst{27-21} = 0b0010111;
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let Inst{20-16} = src1;
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let Inst{12-8} = src2;
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let Inst{7-5} = MinOp;
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let Inst{1-0} = dst;
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}
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class T_fcmp64 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
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: T_fcmp <mnemonic, DoubleRegs, MinOp,
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[(set I1:$dst, (OpNode F64:$src1, F64:$src2))]> {
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let IClass = 0b1101;
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let Inst{27-21} = 0b0010111;
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}
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class T_fcmp32 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
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: T_fcmp <mnemonic, IntRegs, MinOp,
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[(set I1:$dst, (OpNode F32:$src1, F32:$src2))]> {
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let IClass = 0b1100;
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let Inst{27-21} = 0b0111111;
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}
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let isCodeGenOnly = 0 in {
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def F2_dfcmpeq : T_fcmp64<"dfcmp.eq", setoeq, 0b000>;
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def F2_dfcmpgt : T_fcmp64<"dfcmp.gt", setogt, 0b001>;
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def F2_dfcmpge : T_fcmp64<"dfcmp.ge", setoge, 0b010>;
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def F2_dfcmpuo : T_fcmp64<"dfcmp.uo", setuo, 0b011>;
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def F2_sfcmpge : T_fcmp32<"sfcmp.ge", setoge, 0b000>;
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def F2_sfcmpuo : T_fcmp32<"sfcmp.uo", setuo, 0b001>;
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def F2_sfcmpeq : T_fcmp32<"sfcmp.eq", setoeq, 0b011>;
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def F2_sfcmpgt : T_fcmp32<"sfcmp.gt", setogt, 0b100>;
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}
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// F2 convert template classes:
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let Uses = [USR], isFP = 1 in
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class F2_RDD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
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SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
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string chop ="">
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: SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
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"$Rdd = "#mnemonic#"($Rss)"#chop,
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[(set RCOut:$Rdd, (Op RCIn:$Rss))], "",
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S_2op_tc_3or4x_SLOT23> {
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bits<5> Rdd;
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bits<5> Rss;
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let IClass = 0b1000;
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let Inst{27-21} = 0b0000111;
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let Inst{20-16} = Rss;
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let Inst{7-5} = MinOp;
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let Inst{4-0} = Rdd;
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}
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let Uses = [USR], isFP = 1 in
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class F2_RDD_RS_CONVERT<string mnemonic, bits<3> MinOp,
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SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
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string chop ="">
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: SInst <(outs DoubleRegs:$Rdd), (ins IntRegs:$Rs),
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"$Rdd = "#mnemonic#"($Rs)"#chop,
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[(set RCOut:$Rdd, (Op RCIn:$Rs))], "",
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S_2op_tc_3or4x_SLOT23> {
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bits<5> Rdd;
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bits<5> Rs;
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let IClass = 0b1000;
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let Inst{27-21} = 0b0100100;
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let Inst{20-16} = Rs;
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let Inst{7-5} = MinOp;
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let Inst{4-0} = Rdd;
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}
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let Uses = [USR], isFP = 1, hasNewValue = 1 in
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class F2_RD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
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SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
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string chop ="">
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: SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
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"$Rd = "#mnemonic#"($Rss)"#chop,
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[(set RCOut:$Rd, (Op RCIn:$Rss))], "",
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S_2op_tc_3or4x_SLOT23> {
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bits<5> Rd;
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bits<5> Rss;
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let IClass = 0b1000;
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let Inst{27-24} = 0b1000;
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let Inst{23-21} = MinOp;
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let Inst{20-16} = Rss;
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let Inst{7-5} = 0b001;
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let Inst{4-0} = Rd;
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}
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let Uses = [USR], isFP = 1, hasNewValue = 1 in
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class F2_RD_RS_CONVERT<string mnemonic, bits<3> MajOp, bits<3> MinOp,
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SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
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string chop ="">
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: SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
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"$Rd = "#mnemonic#"($Rs)"#chop,
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[(set RCOut:$Rd, (Op RCIn:$Rs))], "",
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S_2op_tc_3or4x_SLOT23> {
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bits<5> Rd;
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bits<5> Rs;
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let IClass = 0b1000;
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let Inst{27-24} = 0b1011;
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let Inst{23-21} = MajOp;
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let Inst{20-16} = Rs;
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let Inst{7-5} = MinOp;
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let Inst{4-0} = Rd;
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}
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// Convert single precision to double precision and vice-versa.
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let isCodeGenOnly = 0 in {
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def F2_conv_sf2df : F2_RDD_RS_CONVERT <"convert_sf2df", 0b000,
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fextend, F64, F32>;
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def F2_conv_df2sf : F2_RD_RSS_CONVERT <"convert_df2sf", 0b000,
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fround, F32, F64>;
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// Convert Integer to Floating Point.
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def F2_conv_d2sf : F2_RD_RSS_CONVERT <"convert_d2sf", 0b010,
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sint_to_fp, F32, I64>;
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def F2_conv_ud2sf : F2_RD_RSS_CONVERT <"convert_ud2sf", 0b001,
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uint_to_fp, F32, I64>;
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def F2_conv_uw2sf : F2_RD_RS_CONVERT <"convert_uw2sf", 0b001, 0b000,
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uint_to_fp, F32, I32>;
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def F2_conv_w2sf : F2_RD_RS_CONVERT <"convert_w2sf", 0b010, 0b000,
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sint_to_fp, F32, I32>;
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def F2_conv_d2df : F2_RDD_RSS_CONVERT <"convert_d2df", 0b011,
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sint_to_fp, F64, I64>;
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def F2_conv_ud2df : F2_RDD_RSS_CONVERT <"convert_ud2df", 0b010,
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uint_to_fp, F64, I64>;
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def F2_conv_uw2df : F2_RDD_RS_CONVERT <"convert_uw2df", 0b001,
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uint_to_fp, F64, I32>;
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def F2_conv_w2df : F2_RDD_RS_CONVERT <"convert_w2df", 0b010,
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sint_to_fp, F64, I32>;
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// Convert Floating Point to Integer - default.
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def F2_conv_df2uw_chop : F2_RD_RSS_CONVERT <"convert_df2uw", 0b101,
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fp_to_uint, I32, F64, ":chop">;
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def F2_conv_df2w_chop : F2_RD_RSS_CONVERT <"convert_df2w", 0b111,
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fp_to_sint, I32, F64, ":chop">;
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def F2_conv_sf2uw_chop : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b001,
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fp_to_uint, I32, F32, ":chop">;
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def F2_conv_sf2w_chop : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b001,
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fp_to_sint, I32, F32, ":chop">;
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def F2_conv_df2d_chop : F2_RDD_RSS_CONVERT <"convert_df2d", 0b110,
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fp_to_sint, I64, F64, ":chop">;
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def F2_conv_df2ud_chop : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b111,
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fp_to_uint, I64, F64, ":chop">;
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def F2_conv_sf2d_chop : F2_RDD_RS_CONVERT <"convert_sf2d", 0b110,
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fp_to_sint, I64, F32, ":chop">;
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def F2_conv_sf2ud_chop : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b101,
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fp_to_uint, I64, F32, ":chop">;
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// Convert Floating Point to Integer: non-chopped.
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let AddedComplexity = 20, Predicates = [HasV5T, IEEERndNearV5T] in {
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def F2_conv_df2d : F2_RDD_RSS_CONVERT <"convert_df2d", 0b000,
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fp_to_sint, I64, F64>;
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def F2_conv_df2ud : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b001,
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fp_to_uint, I64, F64>;
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def F2_conv_sf2ud : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b011,
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fp_to_uint, I64, F32>;
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def F2_conv_sf2d : F2_RDD_RS_CONVERT <"convert_sf2d", 0b100,
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fp_to_sint, I64, F32>;
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def F2_conv_df2uw : F2_RD_RSS_CONVERT <"convert_df2uw", 0b011,
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fp_to_uint, I32, F64>;
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def F2_conv_df2w : F2_RD_RSS_CONVERT <"convert_df2w", 0b100,
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fp_to_sint, I32, F64>;
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def F2_conv_sf2uw : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b000,
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fp_to_uint, I32, F32>;
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def F2_conv_sf2w : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b000,
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fp_to_sint, I32, F32>;
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}
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}
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// Fix up radicand.
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let Uses = [USR], isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
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def F2_sffixupr: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs),
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"$Rd = sffixupr($Rs)",
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[], "" , S_2op_tc_3or4x_SLOT23>, Requires<[HasV5T]> {
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bits<5> Rd;
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bits<5> Rs;
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let IClass = 0b1000;
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let Inst{27-21} = 0b1011101;
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let Inst{20-16} = Rs;
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let Inst{7-5} = 0b000;
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let Inst{4-0} = Rd;
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}
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// F2_sffma: Floating-point fused multiply add.
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let Uses = [USR], isFP = 1, hasNewValue = 1 in
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class T_sfmpy_acc <bit isSub, bit isLib>
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: MInst<(outs IntRegs:$Rx),
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(ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
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"$Rx "#!if(isSub, "-=","+=")#" sfmpy($Rs, $Rt)"#!if(isLib, ":lib",""),
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[], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
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Requires<[HasV5T]> {
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bits<5> Rx;
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bits<5> Rs;
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bits<5> Rt;
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let IClass = 0b1110;
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let Inst{27-21} = 0b1111000;
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let Inst{20-16} = Rs;
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let Inst{13} = 0b0;
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let Inst{12-8} = Rt;
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let Inst{7} = 0b1;
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let Inst{6} = isLib;
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let Inst{5} = isSub;
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let Inst{4-0} = Rx;
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}
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let isCodeGenOnly = 0 in {
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def F2_sffma: T_sfmpy_acc <0, 0>;
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def F2_sffms: T_sfmpy_acc <1, 0>;
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def F2_sffma_lib: T_sfmpy_acc <0, 1>;
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def F2_sffms_lib: T_sfmpy_acc <1, 1>;
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}
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// Floating-point fused multiply add w/ additional scaling (2**pu).
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let Uses = [USR], isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
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def F2_sffma_sc: MInst <
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(outs IntRegs:$Rx),
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(ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt, PredRegs:$Pu),
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"$Rx += sfmpy($Rs, $Rt, $Pu):scale" ,
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[], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
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Requires<[HasV5T]> {
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bits<5> Rx;
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bits<5> Rs;
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bits<5> Rt;
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bits<2> Pu;
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let IClass = 0b1110;
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let Inst{27-21} = 0b1111011;
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let Inst{20-16} = Rs;
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let Inst{13} = 0b0;
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let Inst{12-8} = Rt;
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let Inst{7} = 0b1;
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let Inst{6-5} = Pu;
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let Inst{4-0} = Rx;
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}
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// Convert single precision to double precision and vice-versa.
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def CONVERT_sf2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
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"$dst = convert_sf2df($src)",
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98
test/MC/Disassembler/Hexagon/xtype_fp.txt
Normal file
98
test/MC/Disassembler/Hexagon/xtype_fp.txt
Normal file
@ -0,0 +1,98 @@
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# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
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0x11 0xdf 0x15 0xeb
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# CHECK: r17 = sfadd(r21, r31)
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0x03 0xd5 0xf1 0xc7
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# CHECK: p3 = sfcmp.ge(r17, r21)
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0x23 0xd5 0xf1 0xc7
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# CHECK: p3 = sfcmp.uo(r17, r21)
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0x63 0xd5 0xf1 0xc7
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# CHECK: p3 = sfcmp.eq(r17, r21)
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0x83 0xd5 0xf1 0xc7
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# CHECK: p3 = sfcmp.gt(r17, r21)
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0x03 0xd4 0xf0 0xd2
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# CHECK: p3 = dfcmp.eq(r17:16, r21:20)
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0x23 0xd4 0xf0 0xd2
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# CHECK: p3 = dfcmp.gt(r17:16, r21:20)
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0x43 0xd4 0xf0 0xd2
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# CHECK: p3 = dfcmp.ge(r17:16, r21:20)
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0x63 0xd4 0xf0 0xd2
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# CHECK: p3 = dfcmp.uo(r17:16, r21:20)
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0x10 0xc0 0x95 0x84
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# CHECK: r17:16 = convert_sf2df(r21)
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0x31 0xc0 0x14 0x88
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# CHECK: r17 = convert_df2sf(r21:20)
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0x50 0xc0 0xf4 0x80
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# CHECK: r17:16 = convert_ud2df(r21:20)
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0x70 0xc0 0xf4 0x80
|
||||
# CHECK: r17:16 = convert_d2df(r21:20)
|
||||
0x30 0xc0 0x95 0x84
|
||||
# CHECK: r17:16 = convert_uw2df(r21)
|
||||
0x50 0xc0 0x95 0x84
|
||||
# CHECK: r17:16 = convert_w2df(r21)
|
||||
0x31 0xc0 0x34 0x88
|
||||
# CHECK: r17 = convert_ud2sf(r21:20)
|
||||
0x31 0xc0 0x54 0x88
|
||||
# CHECK: r17 = convert_d2sf(r21:20)
|
||||
0x11 0xc0 0x35 0x8b
|
||||
# CHECK: r17 = convert_uw2sf(r21)
|
||||
0x11 0xc0 0x55 0x8b
|
||||
# CHECK: r17 = convert_w2sf(r21)
|
||||
0x10 0xc0 0xf4 0x80
|
||||
# CHECK: r17:16 = convert_df2d(r21:20)
|
||||
0x30 0xc0 0xf4 0x80
|
||||
# CHECK: r17:16 = convert_df2ud(r21:20)
|
||||
0xd0 0xc0 0xf4 0x80
|
||||
# CHECK: r17:16 = convert_df2d(r21:20):chop
|
||||
0xf0 0xc0 0xf4 0x80
|
||||
# CHECK: r17:16 = convert_df2ud(r21:20):chop
|
||||
0x70 0xc0 0x95 0x84
|
||||
# CHECK: r17:16 = convert_sf2ud(r21)
|
||||
0x90 0xc0 0x95 0x84
|
||||
# CHECK: r17:16 = convert_sf2d(r21)
|
||||
0xb0 0xc0 0x95 0x84
|
||||
# CHECK: r17:16 = convert_sf2ud(r21):chop
|
||||
0xd0 0xc0 0x95 0x84
|
||||
# CHECK: r17:16 = convert_sf2d(r21):chop
|
||||
0x31 0xc0 0x74 0x88
|
||||
# CHECK: r17 = convert_df2uw(r21:20)
|
||||
0x31 0xc0 0x94 0x88
|
||||
# CHECK: r17 = convert_df2w(r21:20)
|
||||
0x31 0xc0 0xb4 0x88
|
||||
# CHECK: r17 = convert_df2uw(r21:20):chop
|
||||
0x31 0xc0 0xf4 0x88
|
||||
# CHECK: r17 = convert_df2w(r21:20):chop
|
||||
0x11 0xc0 0x75 0x8b
|
||||
# CHECK: r17 = convert_sf2uw(r21)
|
||||
0x31 0xc0 0x75 0x8b
|
||||
# CHECK: r17 = convert_sf2uw(r21):chop
|
||||
0x11 0xc0 0x95 0x8b
|
||||
# CHECK: r17 = convert_sf2w(r21)
|
||||
0x31 0xc0 0x95 0x8b
|
||||
# CHECK: r17 = convert_sf2w(r21):chop
|
||||
0x11 0xc0 0xb5 0x8b
|
||||
# CHECK: r17 = sffixupr(r21)
|
||||
0x11 0xdf 0xd5 0xeb
|
||||
# CHECK: r17 = sffixupn(r21, r31)
|
||||
0x31 0xdf 0xd5 0xeb
|
||||
# CHECK: r17 = sffixupd(r21, r31)
|
||||
0x91 0xdf 0x15 0xef
|
||||
# CHECK: r17 += sfmpy(r21, r31)
|
||||
0xb1 0xdf 0x15 0xef
|
||||
# CHECK: r17 -= sfmpy(r21, r31)
|
||||
0xf1 0xdf 0x75 0xef
|
||||
# CHECK: r17 += sfmpy(r21, r31, p3):scale
|
||||
0xd1 0xdf 0x15 0xef
|
||||
# CHECK: r17 += sfmpy(r21, r31):lib
|
||||
0xf1 0xdf 0x15 0xef
|
||||
# CHECK: r17 -= sfmpy(r21, r31):lib
|
||||
0x11 0xdf 0x95 0xeb
|
||||
# CHECK: r17 = sfmax(r21, r31)
|
||||
0x31 0xdf 0x95 0xeb
|
||||
# CHECK: r17 = sfmin(r21, r31)
|
||||
0x11 0xdf 0x55 0xeb
|
||||
# CHECK: r17 = sfmpy(r21, r31)
|
||||
0xf1 0xdf 0xf5 0xeb
|
||||
# CHECK: r17, p3 = sfrecipa(r21, r31)
|
||||
0x31 0xdf 0x15 0xeb
|
||||
# CHECK: r17 = sfsub(r21, r31)
|
||||
Loading…
x
Reference in New Issue
Block a user