From 23329f5e0366af7cd9a96572ed8d6322696e5846 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 16 Aug 2006 07:30:09 +0000 Subject: [PATCH] SelectNodeTo() may return a SDOperand that is different from the input. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29726 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Alpha/AlphaISelDAGToDAG.cpp | 29 ++++++--------- lib/Target/IA64/IA64ISelDAGToDAG.cpp | 51 ++++++++++---------------- lib/Target/Sparc/SparcISelDAGToDAG.cpp | 6 +-- lib/Target/X86/X86ISelDAGToDAG.cpp | 3 +- utils/TableGen/DAGISelEmitter.cpp | 5 +-- 5 files changed, 37 insertions(+), 57 deletions(-) diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 8cc95ab8047..22a99f2abfe 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -197,10 +197,9 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { case ISD::FrameIndex: { int FI = cast(N)->getIndex(); - Result = CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64, - CurDAG->getTargetFrameIndex(FI, MVT::i32), - getI64Imm(0)); - return NULL; + return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64, + CurDAG->getTargetFrameIndex(FI, MVT::i32), + getI64Imm(0)).Val; } case AlphaISD::GlobalBaseReg: Result = getGlobalBaseReg(); @@ -228,8 +227,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { Chain, Chain.getValue(1)); Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64, SDOperand(CNode, 1)); - Result = CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain); - return NULL; + return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain).Val; } case ISD::READCYCLECOUNTER: { @@ -266,24 +264,21 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64); SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg()); - Result = CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, - CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode()); - return NULL; + return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, + CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode()).Val; } case ISD::TargetConstantFP: { ConstantFPSDNode *CN = cast(N); bool isDouble = N->getValueType(0) == MVT::f64; MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32; if (CN->isExactlyValue(+0.0)) { - Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS, - T, CurDAG->getRegister(Alpha::F31, T), - CurDAG->getRegister(Alpha::F31, T)); - return NULL; + return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS, + T, CurDAG->getRegister(Alpha::F31, T), + CurDAG->getRegister(Alpha::F31, T)).Val; } else if ( CN->isExactlyValue(-0.0)) { - Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS, - T, CurDAG->getRegister(Alpha::F31, T), - CurDAG->getRegister(Alpha::F31, T)); - return NULL; + return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS, + T, CurDAG->getRegister(Alpha::F31, T), + CurDAG->getRegister(Alpha::F31, T)).Val; } else { abort(); } diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp index 20a6fd6a44e..b82359ddd51 100644 --- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -398,25 +398,21 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so.. if (cast(N)->isExactlyValue(+0.0)) { - Result = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64); + return CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64).Val; } else if (cast(N)->isExactlyValue(+1.0)) { - Result = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64); + return CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64).Val; } else assert(0 && "Unexpected FP constant!"); - return Result.Val; } case ISD::FrameIndex: { // TODO: reduce creepyness int FI = cast(N)->getIndex(); - if (N->hasOneUse()) { - Result = CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64, - CurDAG->getTargetFrameIndex(FI, MVT::i64)); - return NULL; - } else { - Result = SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64, - CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0); - return Result.Val; - } + if (N->hasOneUse()) + return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64, + CurDAG->getTargetFrameIndex(FI, MVT::i64)).Val; + else + return SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64, + CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0).Val; } case ISD::ConstantPool: { // TODO: nuke the constant pool @@ -467,11 +463,10 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { case MVT::i1: { // this is a bool Opc = IA64::LD1; // first we load a byte, then compare for != 0 if(N->getValueType(0) == MVT::i1) { // XXX: early exit! - Result = CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, + return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0), - CurDAG->getRegister(IA64::r0, MVT::i64), - Chain).getValue(Op.ResNo); - return NULL; + CurDAG->getRegister(IA64::r0, MVT::i64), + Chain).getValue(Op.ResNo).Val; } /* otherwise, we want to load a bool into something bigger: LD1 will do that for us, so we just fall through */ @@ -486,9 +481,8 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { } // TODO: comment this - Result = CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other, - Address, Chain).getValue(Op.ResNo); - return NULL; + return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other, + Address, Chain).getValue(Op.ResNo).Val; } case ISD::TRUNCSTORE: @@ -512,8 +506,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial, CurDAG->getConstant(1, MVT::i64), Tmp), 0); - Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain); - return NULL; + return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain).Val; } case MVT::i64: Opc = IA64::ST8; break; case MVT::f64: Opc = IA64::STF8; break; @@ -531,8 +524,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { SDOperand N1, N2; AddToQueue(N1, N->getOperand(1)); AddToQueue(N2, N->getOperand(2)); - Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain); - return NULL; + return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain).Val; } case ISD::BRCOND: { @@ -542,9 +534,8 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { MachineBasicBlock *Dest = cast(N->getOperand(2))->getBasicBlock(); //FIXME - we do NOT need long branches all the time - Result = CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC, - CurDAG->getBasicBlock(Dest), Chain); - return NULL; + return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC, + CurDAG->getBasicBlock(Dest), Chain).Val; } case ISD::CALLSEQ_START: @@ -554,17 +545,15 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP; SDOperand N0; AddToQueue(N0, N->getOperand(0)); - Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0); - return NULL; + return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0).Val; } case ISD::BR: // FIXME: we don't need long branches all the time! SDOperand N0; AddToQueue(N0, N->getOperand(0)); - Result = CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other, - N->getOperand(1), N0); - return NULL; + return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other, + N->getOperand(1), N0).Val; } return SelectCode(Result, Op); diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 6a94ac2f8eb..fd224703c69 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -1093,8 +1093,8 @@ SDNode *SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { // FIXME: Handle div by immediate. unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; - Result = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); - return NULL; + return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, + TopPart).Val; } case ISD::MULHU: case ISD::MULHS: { @@ -1106,7 +1106,7 @@ SDNode *SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, MulLHS, MulRHS); // The high part is in the Y register. - Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); + return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)).Val; return NULL; } } diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index a5983479a6d..176314a0808 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -703,8 +703,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) { if (C.Val) { if (N.Val->hasOneUse()) { - Result = CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C); - return NULL; + return CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C).Val; } else { SDNode *ResNode = CurDAG->getTargetNode(X86::MOV32ri, MVT::i32, C); Result = SDOperand(ResNode, 0); diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index 191672f6bb8..a3851053c60 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -2794,8 +2794,6 @@ public: if (NodeHasInFlag || HasImpInputs) Code += ", InFlag"; emitCode(Code + ");"); - if (isRoot) - emitCode(" return NULL;"); emitCode("} else {"); emitDecl("ResNode", 1); Code = " ResNode = CurDAG->getTargetNode(Opc" + utostr(OpcNo); @@ -2812,9 +2810,8 @@ public: Code += ", InFlag"; emitCode(Code + ");"); emitCode(" Result = SDOperand(ResNode, 0);"); - if (isRoot) - emitCode(" return Result.Val;"); emitCode("}"); + emitCode("return Result.Val;"); } return std::make_pair(1, ResNo);