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Added VMOVRRS/VMOVSRR to ARMInstrVFP.td for disassembly purpose.

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A8.6.331 VMOV (between two ARM core registers and two single-precision registers)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95548 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2010-02-08 17:26:09 +00:00
parent 7c2da9648c
commit 23401d6f8c
1 changed files with 14 additions and 0 deletions
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14
lib/Target/ARM/ARMInstrVFP.td
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@ -252,6 +252,13 @@ def VMOVRRD : AVConv3I<0b11000101, 0b1011,
let Inst{7-6} = 0b00;
}
def VMOVRRS : AVConv3I<0b11000101, 0b1010,
(outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2),
IIC_VMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
[/* For disassembly only; pattern left blank */]> {
let Inst{7-6} = 0b00;
}
// FMDHR: GPR -> SPR
// FMDLR: GPR -> SPR
@ -262,6 +269,13 @@ def VMOVDRR : AVConv5I<0b11000100, 0b1011,
let Inst{7-6} = 0b00;
}
def VMOVSRR : AVConv5I<0b11000100, 0b1010,
(outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
IIC_VMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
[/* For disassembly only; pattern left blank */]> {
let Inst{7-6} = 0b00;
}
// FMRDH: SPR -> GPR
// FMRDL: SPR -> GPR
// FMRRS: SPR -> GPR