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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-08-14 15:28:20 +00:00
change the fp comparison instructions to not have %st0 explicitly
listed in its asm string, for consistency with the other similar instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118354 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -583,16 +583,16 @@ def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
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def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
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def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
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(outs), (ins RST:$reg),
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(outs), (ins RST:$reg),
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"fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB;
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"fucomi\t$reg">, DB;
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def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
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def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
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(outs), (ins RST:$reg),
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(outs), (ins RST:$reg),
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"fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
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"fucomip\t$reg">, DF;
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}
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}
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def COM_FIr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
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def COM_FIr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
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"fcomi\t{$reg, %st(0)|%ST(0), $reg}">, DB;
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"fcomi\t$reg">, DB;
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def COM_FIPr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
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def COM_FIPr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
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"fcomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
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"fcomip\t$reg">, DF;
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// Floating point flag ops.
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// Floating point flag ops.
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let Defs = [AX] in
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let Defs = [AX] in
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@@ -1377,14 +1377,6 @@ def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
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def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
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def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
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def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
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def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
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// The instruction patterns for these instructions were written with st(0)
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// explicitly in the pattern, match the form with implicit st(0).
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// FIXME: Tweak these to work like fadd etc.
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def : InstAlias<"fcomi $reg", (COM_FIr RST:$reg)>;
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def : InstAlias<"fcomip $reg", (COM_FIPr RST:$reg)>;
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def : InstAlias<"fucomi $reg", (UCOM_FIr RST:$reg)>;
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def : InstAlias<"fucomip $reg", (UCOM_FIPr RST:$reg)>;
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// Various unary fpstack operations default to operating on on ST1.
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// Various unary fpstack operations default to operating on on ST1.
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// For example, "fxch" -> "fxch %st(1)"
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// For example, "fxch" -> "fxch %st(1)"
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def : InstAlias<"faddp", (ADD_FPrST0 ST1)>;
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def : InstAlias<"faddp", (ADD_FPrST0 ST1)>;
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@@ -1422,6 +1414,11 @@ defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
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defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
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defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
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defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
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defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
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defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
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defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
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defm : FpUnaryAlias<"fcomi", COM_FIr>;
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defm : FpUnaryAlias<"fcomip", COM_FIPr>;
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defm : FpUnaryAlias<"fucomi", UCOM_FIr>;
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defm : FpUnaryAlias<"fucomip", UCOM_FIPr>;
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// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
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// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
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// commute. We also allow fdivrp/fsubrp even though they don't commute, solely
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// commute. We also allow fdivrp/fsubrp even though they don't commute, solely
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@@ -4474,19 +4474,19 @@
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// CHECK: encoding: [0xdb,0xda]
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// CHECK: encoding: [0xdb,0xda]
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fcmovnu %st(2),%st
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fcmovnu %st(2),%st
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// CHECK: fcomi %st(2), %st(0)
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// CHECK: fcomi %st(2)
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// CHECK: encoding: [0xdb,0xf2]
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// CHECK: encoding: [0xdb,0xf2]
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fcomi %st(2),%st
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fcomi %st(2),%st
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// CHECK: fucomi %st(2), %st(0)
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// CHECK: fucomi %st(2)
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// CHECK: encoding: [0xdb,0xea]
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// CHECK: encoding: [0xdb,0xea]
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fucomi %st(2),%st
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fucomi %st(2),%st
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// CHECK: fcomip %st(2), %st(0)
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// CHECK: fcomip %st(2)
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// CHECK: encoding: [0xdf,0xf2]
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// CHECK: encoding: [0xdf,0xf2]
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fcomip %st(2),%st
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fcomip %st(2),%st
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// CHECK: fucomip %st(2), %st(0)
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// CHECK: fucomip %st(2)
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// CHECK: encoding: [0xdf,0xea]
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// CHECK: encoding: [0xdf,0xea]
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fucomip %st(2),%st
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fucomip %st(2),%st
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@@ -14150,16 +14150,16 @@
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// CHECK: fcmovnu %st(2), %st(0)
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// CHECK: fcmovnu %st(2), %st(0)
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fcmovnu %st(2),%st
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fcmovnu %st(2),%st
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// CHECK: fcomi %st(2), %st(0)
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// CHECK: fcomi %st(2)
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fcomi %st(2),%st
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fcomi %st(2),%st
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// CHECK: fucomi %st(2), %st(0)
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// CHECK: fucomi %st(2)
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fucomi %st(2),%st
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fucomi %st(2),%st
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// CHECK: fcomip %st(2), %st(0)
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// CHECK: fcomip %st(2)
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fcomip %st(2),%st
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fcomip %st(2),%st
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// CHECK: fucomip %st(2), %st(0)
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// CHECK: fucomip %st(2)
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fucomip %st(2),%st
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fucomip %st(2),%st
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// CHECK: movnti %ecx, 3735928559(%ebx,%ecx,8)
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// CHECK: movnti %ecx, 3735928559(%ebx,%ecx,8)
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@@ -708,27 +708,27 @@ pshufw $90, %mm4, %mm0
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// CHECK: encoding: [0x0f,0x01,0x48,0x04]
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// CHECK: encoding: [0x0f,0x01,0x48,0x04]
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sidtl 4(%eax)
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sidtl 4(%eax)
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// CHECK: fcomip %st(2), %st(0)
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// CHECK: fcomip %st(2)
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// CHECK: encoding: [0xdf,0xf2]
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// CHECK: encoding: [0xdf,0xf2]
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fcompi %st(2),%st
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fcompi %st(2),%st
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// CHECK: fcomip %st(2), %st(0)
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// CHECK: fcomip %st(2)
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// CHECK: encoding: [0xdf,0xf2]
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// CHECK: encoding: [0xdf,0xf2]
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fcompi %st(2)
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fcompi %st(2)
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// CHECK: fcomip %st(1), %st(0)
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// CHECK: fcomip %st(1)
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// CHECK: encoding: [0xdf,0xf1]
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// CHECK: encoding: [0xdf,0xf1]
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fcompi
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fcompi
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// CHECK: fucomip %st(2), %st(0)
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// CHECK: fucomip %st(2)
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// CHECK: encoding: [0xdf,0xea]
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// CHECK: encoding: [0xdf,0xea]
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fucompi %st(2),%st
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fucompi %st(2),%st
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// CHECK: fucomip %st(2), %st(0)
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// CHECK: fucomip %st(2)
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// CHECK: encoding: [0xdf,0xea]
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// CHECK: encoding: [0xdf,0xea]
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fucompi %st(2)
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fucompi %st(2)
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// CHECK: fucomip %st(1), %st(0)
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// CHECK: fucomip %st(1)
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// CHECK: encoding: [0xdf,0xe9]
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// CHECK: encoding: [0xdf,0xe9]
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fucompi
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fucompi
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@@ -261,11 +261,11 @@ fmulp
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fdivp
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fdivp
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fdivrp
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fdivrp
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// CHECK: fcomi %st(1), %st(0)
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// CHECK: fcomi %st(1)
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// CHECK: fcomi %st(2), %st(0)
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// CHECK: fcomi %st(2)
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// CHECK: fucomi %st(1), %st(0)
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// CHECK: fucomi %st(1)
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// CHECK: fucomi %st(2), %st(0)
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// CHECK: fucomi %st(2)
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// CHECK: fucomi %st(2), %st(0)
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// CHECK: fucomi %st(2)
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fcomi
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fcomi
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fcomi %st(2)
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fcomi %st(2)
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