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Fix PR5410: LiveVariables lost subreg def:

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D0<def,dead> = ...
...
             = S0<use, kill>
S0<def>      = ...
...
D0<def>      = 

The first D0 def is correctly marked dead, however, livevariables should have
added an implicit def of S0 or we end up with a use without a def.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88690 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-11-13 20:36:40 +00:00
parent 87d21b92fc
commit 236490d870
2 changed files with 27 additions and 1 deletions
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8
lib/CodeGen/LiveVariables.cpp
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@ -230,8 +230,9 @@ MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
/// implicit defs to a machine instruction if there was an earlier def of its /// implicit defs to a machine instruction if there was an earlier def of its
/// super-register. /// super-register.
void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
MachineInstr *LastDef = PhysRegDef[Reg];
// If there was a previous use or a "full" def all is well. // If there was a previous use or a "full" def all is well.
if (!PhysRegDef[Reg] && !PhysRegUse[Reg]) { if (!LastDef && !PhysRegUse[Reg]) {
// Otherwise, the last sub-register def implicitly defines this register. // Otherwise, the last sub-register def implicitly defines this register.
// e.g. // e.g.
// AH = // AH =
@ -265,6 +266,11 @@ void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
} }
} }
} }
else if (LastDef && !PhysRegUse[Reg] &&
!LastDef->findRegisterDefOperand(Reg))
// Last def defines the super register, add an implicit def of reg.
LastDef->addOperand(MachineOperand::CreateReg(Reg,
true/*IsDef*/, true/*IsImp*/));
// Remember this use. // Remember this use.
PhysRegUse[Reg] = MI; PhysRegUse[Reg] = MI;

20
test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll Normal file
View File

@ -0,0 +1,20 @@
; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
; PR5410
%0 = type { float, float, float, float }
%pln = type { %vec, float }
%vec = type { [4 x float] }
define arm_aapcs_vfpcc float @aaa(%vec* nocapture %ustart, %vec* nocapture %udir, %vec* nocapture %vstart, %vec* nocapture %vdir, %vec* %upoint, %vec* %vpoint) {
entry:
br i1 undef, label %bb81, label %bb48
bb48: ; preds = %entry
%0 = call arm_aapcs_vfpcc %0 @bbb(%pln* undef, %vec* %vstart, %vec* undef) nounwind ; <%0> [#uses=0]
ret float 0.000000e+00
bb81: ; preds = %entry
ret float 0.000000e+00
}
declare arm_aapcs_vfpcc %0 @bbb(%pln* nocapture, %vec* nocapture, %vec* nocapture) nounwind