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Match operand naming to allow correct decoding of t2LDRSH_POST.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138298 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-08-22 23:22:05 +00:00
parent 2026de255e
commit 2379fc235f
2 changed files with 5 additions and 2 deletions
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4
lib/Target/ARM/ARMInstrThumb2.td
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@ -1238,10 +1238,10 @@ def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
"ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
[]>;
def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$Rn),
def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
(ins GPR:$base, t2am_imm8_offset:$addr),
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
"ldrsh", "\t$dst, [$Rn], $addr", "$base = $Rn",
"ldrsh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
[]>;
} // mayLoad = 1, neverHasSideEffects = 1

3
test/MC/Disassembler/ARM/thumb-tests.txt
View File

@ -277,3 +277,6 @@
# CHECK: and.w r5, r1, r10, ror #7
0x1 0xea 0xfa 0x95
# CHECK: ldrsh r6, [sp], #81
0x3d 0xf9 0x51 0x6b