mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
Handle regmask operands in ARMInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150833 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
fc0d7400bc
commit
2420b558de
@ -503,15 +503,11 @@ SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
|
||||
|
||||
bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
|
||||
std::vector<MachineOperand> &Pred) const {
|
||||
// FIXME: This confuses implicit_def with optional CPSR def.
|
||||
const MCInstrDesc &MCID = MI->getDesc();
|
||||
if (!MCID.getImplicitDefs() && !MI->hasOptionalDef())
|
||||
return false;
|
||||
|
||||
bool Found = false;
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
const MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
|
||||
if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
|
||||
(MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
|
||||
Pred.push_back(MO);
|
||||
Found = true;
|
||||
}
|
||||
@ -1797,6 +1793,8 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
|
||||
|
||||
for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
|
||||
const MachineOperand &MO = Instr.getOperand(IO);
|
||||
if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR))
|
||||
return false;
|
||||
if (!MO.isReg()) continue;
|
||||
|
||||
// This instruction modifies or uses CPSR after the one we want to
|
||||
@ -1858,6 +1856,10 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
|
||||
for (unsigned IO = 0, EO = Instr.getNumOperands();
|
||||
!isSafe && IO != EO; ++IO) {
|
||||
const MachineOperand &MO = Instr.getOperand(IO);
|
||||
if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
|
||||
isSafe = true;
|
||||
break;
|
||||
}
|
||||
if (!MO.isReg() || MO.getReg() != ARM::CPSR)
|
||||
continue;
|
||||
if (MO.isDef()) {
|
||||
|
@ -586,7 +586,7 @@ Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
|
||||
ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
|
||||
if (!(NCC == CC || NCC == OCC) ||
|
||||
NMI->modifiesRegister(SrcReg, &TRI) ||
|
||||
NMI->definesRegister(ARM::CPSR))
|
||||
NMI->modifiesRegister(ARM::CPSR, &TRI))
|
||||
break;
|
||||
if (++NumInsts == 4)
|
||||
// Too many in a row!
|
||||
|
Loading…
Reference in New Issue
Block a user