6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-15 09:33:39 +00:00
Code Issues Projects Releases Wiki Activity

adjust the instruction ordering in some PPC tests: changes due to postRA haz. rec.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145678 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2011-12-02 04:58:12 +00:00
parent db809e0eb7
commit 2457544630
4 changed files with 23 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
test/CodeGen/PowerPC/2010-02-12-saveCR.ll
View File

@ -7,8 +7,8 @@ target triple = "powerpc-apple-darwin9.6"
define void @foo() nounwind { define void @foo() nounwind {
entry: entry:
;CHECK: mfcr r2 ;CHECK: mfcr r2
;CHECK: rlwinm r2, r2, 8, 0, 31
;CHECK: lis r0, 1 ;CHECK: lis r0, 1
;CHECK: rlwinm r2, r2, 8, 0, 31
;CHECK: ori r0, r0, 34540 ;CHECK: ori r0, r0, 34540
;CHECK: stwx r2, r1, r0 ;CHECK: stwx r2, r1, r0
%x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1] %x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]

15
test/CodeGen/PowerPC/Frames-large.ll
View File

@ -15,18 +15,20 @@ define i32* @f1() nounwind {
; PPC32-NOFP: _f1: ; PPC32-NOFP: _f1:
; PPC32-NOFP: lis r0, -1 ; PPC32-NOFP: lis r0, -1
; PPC32-NOFP: addi r3, r1, 68
; PPC32-NOFP: ori r0, r0, 32704 ; PPC32-NOFP: ori r0, r0, 32704
; PPC32-NOFP: stwux r1, r1, r0 ; PPC32-NOFP: stwux r1, r1, r0
; PPC32-NOFP: addi r3, r1, 68
; PPC32-NOFP: lwz r1, 0(r1) ; PPC32-NOFP: lwz r1, 0(r1)
; PPC32-NOFP: blr ; PPC32-NOFP: blr
; PPC32-FP: _f1: ; PPC32-FP: _f1:
; PPC32-FP: stw r31, -4(r1)
; PPC32-FP: lis r0, -1 ; PPC32-FP: lis r0, -1
; PPC32-FP: stw r31, -4(r1)
; PPC32-FP: mr r31, r1
; PPC32-FP: ori r0, r0, 32704 ; PPC32-FP: ori r0, r0, 32704
; PPC32-FP: addi r3, r31, 64
; PPC32-FP: stwux r1, r1, r0 ; PPC32-FP: stwux r1, r1, r0
; ...
; PPC32-FP: lwz r1, 0(r1) ; PPC32-FP: lwz r1, 0(r1)
; PPC32-FP: lwz r31, -4(r1) ; PPC32-FP: lwz r31, -4(r1)
; PPC32-FP: blr ; PPC32-FP: blr
@ -34,19 +36,20 @@ define i32* @f1() nounwind {
; PPC64-NOFP: _f1: ; PPC64-NOFP: _f1:
; PPC64-NOFP: lis r0, -1 ; PPC64-NOFP: lis r0, -1
; PPC64-NOFP: addi r3, r1, 116
; PPC64-NOFP: ori r0, r0, 32656 ; PPC64-NOFP: ori r0, r0, 32656
; PPC64-NOFP: stdux r1, r1, r0 ; PPC64-NOFP: stdux r1, r1, r0
; PPC64-NOFP: addi r3, r1, 116
; PPC64-NOFP: ld r1, 0(r1) ; PPC64-NOFP: ld r1, 0(r1)
; PPC64-NOFP: blr ; PPC64-NOFP: blr
; PPC64-FP: _f1: ; PPC64-FP: _f1:
; PPC64-FP: std r31, -8(r1)
; PPC64-FP: lis r0, -1 ; PPC64-FP: lis r0, -1
; PPC64-FP: std r31, -8(r1)
; PPC64-FP: mr r31, r1
; PPC64-FP: ori r0, r0, 32640 ; PPC64-FP: ori r0, r0, 32640
; PPC64-FP: addi r3, r31, 124
; PPC64-FP: stdux r1, r1, r0 ; PPC64-FP: stdux r1, r1, r0
; ...
; PPC64-FP: ld r1, 0(r1) ; PPC64-FP: ld r1, 0(r1)
; PPC64-FP: ld r31, -8(r1) ; PPC64-FP: ld r31, -8(r1)
; PPC64-FP: blr ; PPC64-FP: blr

2
test/CodeGen/PowerPC/big-endian-formal-args.ll
View File

@ -2,8 +2,8 @@
declare void @bar(i64 %x, i64 %y) declare void @bar(i64 %x, i64 %y)
; CHECK: li 4, 2
; CHECK: li {{[53]}}, 0 ; CHECK: li {{[53]}}, 0
; CHECK: li 4, 2
; CHECK: li 6, 3 ; CHECK: li 6, 3
; CHECK: mr {{[53]}}, {{[53]}} ; CHECK: mr {{[53]}}, {{[53]}}

12
test/CodeGen/PowerPC/indirectbr.ll
View File

@ -17,10 +17,22 @@ entry:
bb2: ; preds = %entry, %bb3 bb2: ; preds = %entry, %bb3
%gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1] %gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1]
; PIC: mtctr ; PIC: mtctr
; PIC-NEXT: li
; PIC-NEXT: li
; PIC-NEXT: li
; PIC-NEXT: li
; PIC-NEXT: bctr ; PIC-NEXT: bctr
; STATIC: mtctr ; STATIC: mtctr
; STATIC-NEXT: li
; STATIC-NEXT: li
; STATIC-NEXT: li
; STATIC-NEXT: li
; STATIC-NEXT: bctr ; STATIC-NEXT: bctr
; PPC64: mtctr ; PPC64: mtctr
; PPC64-NEXT: li
; PPC64-NEXT: li
; PPC64-NEXT: li
; PPC64-NEXT: li
; PPC64-NEXT: bctr ; PPC64-NEXT: bctr
indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1] indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]