diff --git a/lib/Transforms/Vectorize/SLPVectorizer.cpp b/lib/Transforms/Vectorize/SLPVectorizer.cpp
index f6b5b122742..ee322279df3 100644
--- a/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -955,11 +955,11 @@ void BoUpSLP::buildTree_rec(ArrayRef<Value *> VL, unsigned Depth) {
         return;
       }
 
-      Intrinsic::ID ID = II->getIntrinsicID();
+      Function *Int = II->getCalledFunction();
 
       for (unsigned i = 1, e = VL.size(); i != e; ++i) {
         IntrinsicInst *II2 = dyn_cast<IntrinsicInst>(VL[i]);
-        if (!II2 || II2->getIntrinsicID() != ID) {
+        if (!II2 || II2->getCalledFunction() != Int) {
           newTreeEntry(VL, false);
           DEBUG(dbgs() << "SLP: mismatched calls:" << *II << "!=" << *VL[i]
                        << "\n");
diff --git a/test/Transforms/SLPVectorizer/ARM64/lit.local.cfg b/test/Transforms/SLPVectorizer/ARM64/lit.local.cfg
new file mode 100644
index 00000000000..84ac9811f01
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/ARM64/lit.local.cfg
@@ -0,0 +1,3 @@
+targets = set(config.root.targets_to_build.split())
+if not 'ARM64' in targets:
+    config.unsupported = True
diff --git a/test/Transforms/SLPVectorizer/ARM64/mismatched-intrinsics.ll b/test/Transforms/SLPVectorizer/ARM64/mismatched-intrinsics.ll
new file mode 100644
index 00000000000..3d6da124fc4
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/ARM64/mismatched-intrinsics.ll
@@ -0,0 +1,18 @@
+; RUN: opt -S -slp-vectorizer %s | FileCheck %s
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-apple-ios5.0.0"
+
+define i64 @mismatched_intrinsics(<4 x i32> %in1, <2 x i32> %in2) nounwind {
+; CHECK-LABEL: @mismatched_intrinsics
+; CHECK: call i64 @llvm.arm64.neon.saddlv.i64.v4i32
+; CHECK: call i64 @llvm.arm64.neon.saddlv.i64.v2i32
+
+  %vaddlvq_s32.i = tail call i64 @llvm.arm64.neon.saddlv.i64.v4i32(<4 x i32> %in1) #2
+  %vaddlv_s32.i = tail call i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32> %in2) #2
+  %tst = icmp sgt i64 %vaddlvq_s32.i, %vaddlv_s32.i
+  %equal = sext i1 %tst to i64
+  ret i64 %equal
+}
+
+declare i64 @llvm.arm64.neon.saddlv.i64.v4i32(<4 x i32> %in1)
+declare i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32> %in1)