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[PATCH, PowerPC] Accept 'U' and 'X' constraints in inline asm

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Inline asm may specify 'U' and 'X' constraints to print a 'u' for an
update-form memory reference, or an 'x' for an indexed-form memory
reference.  However, these are really only useful in GCC internal code
generation.  In inline asm the operand of the memory constraint is
typically just a register containing the address, so 'U' and 'X' make
no sense.

This patch quietly accepts 'U' and 'X' in inline asm patterns, but
otherwise does nothing.  If we ever unexpectedly see a non-register,
we'll assert and sort it out afterwards.

I've added a new test for these constraints; the test case should be
used for other asm-constraints changes down the road.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217622 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Schmidt 2014-09-11 20:10:03 +00:00
parent 67868b5791
commit 24ebd0edd6
2 changed files with 42 additions and 0 deletions
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10
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -275,6 +275,16 @@ bool PPCAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
printOperand(MI, OpNo, O);
return false;
}
case 'U': // Print 'u' for update form.
case 'X': // Print 'x' for indexed form.
{
// Memory constraints should always produce an MO_Register,
// so we never get an update or indexed form. (In GCC, these
// are useful in internal code gen; not so much in inline asm.)
// So tolerate these but don't output anything.
assert(MI->getOperand(OpNo).isReg());
return false;
}
}
}

32
test/CodeGen/PowerPC/asm-constraints.ll Normal file
View File

@ -0,0 +1,32 @@
; RUN llc < %s -mcpu=pwr8 | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
; Function Attrs: nounwind
; Check that we accept 'U' and 'X' constraints.
define void @foo(i32 signext %result, i8* %addr) #0 {
entry:
%result.addr = alloca i32, align 4
%addr.addr = alloca i8*, align 8
store i32 %result, i32* %result.addr, align 4
store i8* %addr, i8** %addr.addr, align 8
%0 = load i8** %addr.addr, align 8
%1 = call i32 asm sideeffect "ld${1:U}${1:X} $0,$1\0Acmpw $0,$0\0Abne- 1f\0A1: isync\0A", "=r,*m,~{memory},~{cr0}"(i8* %0) #1, !srcloc !1
store i32 %1, i32* %result.addr, align 4
ret void
}
; CHECK-LABEL: @foo
; CHECK: ld [[REG:[0-9]+]],0(4)
; CHECK-NEXT: cmpw [[REG]],[[REG]]
; CHECK-NEXT: bne- 1f
; CHECK-NEXT: 1: isync
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind }
!llvm.ident = !{!0}
!0 = metadata !{metadata !"clang version 3.6.0 (trunk 217557)"}
!1 = metadata !{i32 67, i32 91, i32 110, i32 126}