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Revert 132424 to fix PR10068.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132479 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola
2011-06-02 19:57:47 +00:00
parent 552c0ee4f9
commit 251b4a0405
9 changed files with 22 additions and 152 deletions
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9
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@@ -1759,14 +1759,13 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
Op.getOperand(0).getValueType().isFloatingPoint() &&
!Op.getOperand(0).getValueType().isVector()) {
bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
if (OpVTLegal || i32Legal) {
EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
if (isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32)) {
EVT Ty = (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) ?
Op.getValueType() : MVT::i32;
// Make a FGETSIGN + SHL to move the sign bit into the appropriate
// place. We expect the SHL to be eliminated by other optimizations.
SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
if (!OpVTLegal)
if (Ty != Op.getValueType())
Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
unsigned ShVal = Op.getValueType().getSizeInBits()-1;
SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());