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[ARM64] Fix materialization of an fp128 zero immediate. There currently

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is not a pattern to lower this with clever instructions that zero the
register, so restrict the zero immediate legality special case to f64
and f32 (the only two sizes which fmov seems to directly support). Fixes
backend errors when building code such as libxml.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205161 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth 2014-03-31 00:02:10 +00:00
parent cb1800772a
commit 2530cd31f4
2 changed files with 14 additions and 2 deletions
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5
lib/Target/ARM64/ARM64ISelLowering.cpp
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@ -3879,8 +3879,9 @@ ARM64TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
}
bool ARM64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
// We can materialize #0.0 as fmov $Rd, XZR.
if (Imm.isPosZero())
// We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
// FIXME: We should be able to handle f128 as well with a clever lowering.
if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
return true;
if (VT == MVT::f64)

11
test/CodeGen/ARM64/fp-imm.ll
View File

@ -19,3 +19,14 @@ define float @bar() {
; CHECK-NEXT: ret
ret float 0x400921FB60000000
}
; CHECK: literal16
; CHECK: .quad 0
; CHECK: .quad 0
define fp128 @baz() {
; CHECK: _baz:
; CHECK: adrp x[[REG:[0-9]+]], lCPI2_0@PAGE
; CHECK: ldr q0, [x[[REG]], lCPI2_0@PAGEOFF]
; CHECK-NEXT: ret
ret fp128 0xL00000000000000000000000000000000
}