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Only enable 64-bit bswap DAG combines for PPC64
Compiling in 32-bit mode on a P7 would assert after 64-bit DAG combines were added for bswap with load/store. This is because these combines are really only valid in 64-bit mode, regardless of the CPU (and this was not being checked). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178286 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -6606,6 +6606,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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(N->getOperand(1).getValueType() == MVT::i32 ||
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N->getOperand(1).getValueType() == MVT::i16 ||
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(TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
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TM.getSubtarget<PPCSubtarget>().isPPC64() &&
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N->getOperand(1).getValueType() == MVT::i64))) {
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SDValue BSwapOp = N->getOperand(1).getOperand(0);
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// Do an any-extend to 32-bits if this is a half-word input.
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@ -6629,6 +6630,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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N->getOperand(0).hasOneUse() &&
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(N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
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(TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
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TM.getSubtarget<PPCSubtarget>().isPPC64() &&
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N->getValueType(0) == MVT::i64))) {
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SDValue Load = N->getOperand(0);
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LoadSDNode *LD = cast<LoadSDNode>(Load);
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@ -1,6 +1,7 @@
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; RUN: llc < %s -march=ppc32 | FileCheck %s -check-prefix=X32
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; RUN: llc < %s -march=ppc64 | FileCheck %s -check-prefix=X64
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; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s -check-prefix=PWR7
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; RUN: llc < %s -march=ppc32 -mcpu=pwr7 | FileCheck %s -check-prefix=X32
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define void @STWBRX(i32 %i, i8* %ptr, i32 %off) {
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