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https://github.com/c64scene-ar/llvm-6502.git
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R600: Custom lower frem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217553 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
3b670550ad
commit
257e85e7c2
@ -130,6 +130,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::FROUND, MVT::f32, Legal);
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setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
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setOperationAction(ISD::FREM, MVT::f32, Custom);
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setOperationAction(ISD::FREM, MVT::f64, Custom);
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// Lower floating point store/load to integer store/load to reduce the number
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// of patterns in tablegen.
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setOperationAction(ISD::STORE, MVT::f32, Promote);
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@ -347,6 +350,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::FDIV, VT, Expand);
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setOperationAction(ISD::FEXP2, VT, Expand);
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setOperationAction(ISD::FLOG2, VT, Expand);
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setOperationAction(ISD::FREM, VT, Expand);
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setOperationAction(ISD::FPOW, VT, Expand);
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setOperationAction(ISD::FFLOOR, VT, Expand);
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setOperationAction(ISD::FTRUNC, VT, Expand);
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@ -548,6 +552,7 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
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case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
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case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
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case ISD::FREM: return LowerFREM(Op, DAG);
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case ISD::FCEIL: return LowerFCEIL(Op, DAG);
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case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
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case ISD::FRINT: return LowerFRINT(Op, DAG);
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@ -1650,6 +1655,20 @@ SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
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return DAG.getMergeValues(Res, DL);
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}
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// (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
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SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
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SDLoc SL(Op);
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EVT VT = Op.getValueType();
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SDValue X = Op.getOperand(0);
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SDValue Y = Op.getOperand(1);
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SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
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SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
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SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
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return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
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}
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SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
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SDLoc SL(Op);
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SDValue Src = Op.getOperand(0);
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@ -44,6 +44,7 @@ private:
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/// \returns The resulting chain.
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SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
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103
test/CodeGen/R600/frem.ll
Normal file
103
test/CodeGen/R600/frem.ll
Normal file
@ -0,0 +1,103 @@
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; RUN: llc -march=r600 -mcpu=SI -enable-misched < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; FUNC-LABEL: @frem_f32:
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; SI-DAG: BUFFER_LOAD_DWORD [[X:v[0-9]+]], {{.*$}}
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; SI-DAG: BUFFER_LOAD_DWORD [[Y:v[0-9]+]], {{.*}} offset:0x10
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; SI-DAG: V_CMP
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; SI-DAG: V_MUL_F32
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; SI: V_RCP_F32_e32
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; SI: V_MUL_F32_e32
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; SI: V_MUL_F32_e32
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; SI: V_TRUNC_F32_e32
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; SI: V_MAD_F32
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; SI: S_ENDPGM
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define void @frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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float addrspace(1)* %in2) #0 {
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%gep2 = getelementptr float addrspace(1)* %in2, i32 4
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%r0 = load float addrspace(1)* %in1, align 4
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%r1 = load float addrspace(1)* %gep2, align 4
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%r2 = frem float %r0, %r1
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store float %r2, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @unsafe_frem_f32:
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; SI: BUFFER_LOAD_DWORD [[Y:v[0-9]+]], {{.*}} offset:0x10
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; SI: BUFFER_LOAD_DWORD [[X:v[0-9]+]], {{.*}}
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; SI: V_RCP_F32_e32 [[INVY:v[0-9]+]], [[Y]]
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; SI: V_MUL_F32_e32 [[DIV:v[0-9]+]], [[INVY]], [[X]]
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; SI: V_TRUNC_F32_e32 [[TRUNC:v[0-9]+]], [[DIV]]
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; SI: V_MAD_F32 [[RESULT:v[0-9]+]], -[[TRUNC]], [[Y]], [[X]],
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; SI: BUFFER_STORE_DWORD [[RESULT]]
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; SI: S_ENDPGM
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define void @unsafe_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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float addrspace(1)* %in2) #1 {
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%gep2 = getelementptr float addrspace(1)* %in2, i32 4
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%r0 = load float addrspace(1)* %in1, align 4
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%r1 = load float addrspace(1)* %gep2, align 4
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%r2 = frem float %r0, %r1
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store float %r2, float addrspace(1)* %out, align 4
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ret void
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}
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; TODO: This should check something when f64 fdiv is implemented
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; correctly
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; FUNC-LABEL: @frem_f64:
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; SI: S_ENDPGM
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define void @frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) #0 {
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%r0 = load double addrspace(1)* %in1, align 8
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%r1 = load double addrspace(1)* %in2, align 8
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%r2 = frem double %r0, %r1
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store double %r2, double addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @unsafe_frem_f64:
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; SI: V_RCP_F64_e32
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; SI: V_MUL_F64
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; SI: V_BFE_I32
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; SI: V_FMA_F64
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; SI: S_ENDPGM
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define void @unsafe_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) #1 {
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%r0 = load double addrspace(1)* %in1, align 8
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%r1 = load double addrspace(1)* %in2, align 8
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%r2 = frem double %r0, %r1
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store double %r2, double addrspace(1)* %out, align 8
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ret void
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}
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define void @frem_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in1,
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<2 x float> addrspace(1)* %in2) #0 {
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%gep2 = getelementptr <2 x float> addrspace(1)* %in2, i32 4
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%r0 = load <2 x float> addrspace(1)* %in1, align 8
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%r1 = load <2 x float> addrspace(1)* %gep2, align 8
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%r2 = frem <2 x float> %r0, %r1
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store <2 x float> %r2, <2 x float> addrspace(1)* %out, align 8
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ret void
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}
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define void @frem_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in1,
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<4 x float> addrspace(1)* %in2) #0 {
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%gep2 = getelementptr <4 x float> addrspace(1)* %in2, i32 4
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%r0 = load <4 x float> addrspace(1)* %in1, align 16
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%r1 = load <4 x float> addrspace(1)* %gep2, align 16
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%r2 = frem <4 x float> %r0, %r1
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store <4 x float> %r2, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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define void @frem_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1,
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<2 x double> addrspace(1)* %in2) #0 {
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%gep2 = getelementptr <2 x double> addrspace(1)* %in2, i32 4
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%r0 = load <2 x double> addrspace(1)* %in1, align 16
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%r1 = load <2 x double> addrspace(1)* %gep2, align 16
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%r2 = frem <2 x double> %r0, %r1
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store <2 x double> %r2, <2 x double> addrspace(1)* %out, align 16
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ret void
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}
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attributes #0 = { nounwind "unsafe-fp-math"="false" }
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attributes #1 = { nounwind "unsafe-fp-math"="true" }
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