diff --git a/lib/Target/PowerPC/PPCCallingConv.td b/lib/Target/PowerPC/PPCCallingConv.td index 6b6ae0778e8..9f916f38d5e 100644 --- a/lib/Target/PowerPC/PPCCallingConv.td +++ b/lib/Target/PowerPC/PPCCallingConv.td @@ -23,7 +23,7 @@ class CCIfSubtarget // Return-value convention for PowerPC def RetCC_PPC : CallingConv<[ CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>, - CCIfType<[i64], CCAssignToReg<[X3, X4]>>, + CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>, CCIfType<[f32], CCAssignToReg<[F1]>>, CCIfType<[f64], CCAssignToReg<[F1, F2]>>, diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index c6885cf7b8a..88d4b5f63d7 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2259,7 +2259,24 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, NodeTys.push_back(MVT::i32); break; case MVT::i64: - if (Op.Val->getValueType(1) == MVT::i64) { + if (Op.Val->getNumValues()>=4 && + Op.Val->getValueType(3) == MVT::i64) { + Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); + ResultVals[0] = Chain.getValue(0); + Chain = DAG.getCopyFromReg(Chain, PPC::X4, MVT::i64, + Chain.getValue(2)).getValue(1); + ResultVals[1] = Chain.getValue(0); + Chain = DAG.getCopyFromReg(Chain, PPC::X5, MVT::i64, + Chain.getValue(2)).getValue(1); + ResultVals[2] = Chain.getValue(0); + Chain = DAG.getCopyFromReg(Chain, PPC::X6, MVT::i64, + Chain.getValue(2)).getValue(1); + ResultVals[3] = Chain.getValue(0); + NumResults = 4; + NodeTys.push_back(MVT::i64); + NodeTys.push_back(MVT::i64); + NodeTys.push_back(MVT::i64); + } else if (Op.Val->getValueType(1) == MVT::i64) { Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); Chain = DAG.getCopyFromReg(Chain, PPC::X4, MVT::i64,