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[mips] Fix ll and sc instructions

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Summary: The ll and sc instructions for r6 and non-r6 are misplaced. This patch fixes that.

Patch by Jyun-Yan You

Differential Revision: http://reviews.llvm.org/D4578


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213847 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2014-07-24 09:47:14 +00:00
parent de929f8b7d
commit 25f4fcd8e0
1 changed files with 4 additions and 4 deletions
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8
lib/Target/Mips/MipsISelLowering.cpp
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@ -969,16 +969,16 @@ MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
LL = Mips::LL_MM;
SC = Mips::SC_MM;
} else {
LL = Subtarget.hasMips32r6() ? Mips::LL : Mips::LL_R6;
SC = Subtarget.hasMips32r6() ? Mips::SC : Mips::SC_R6;
LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
}
AND = Mips::AND;
NOR = Mips::NOR;
ZERO = Mips::ZERO;
BEQ = Mips::BEQ;
} else {
LL = Subtarget.hasMips64r6() ? Mips::LLD : Mips::LLD_R6;
SC = Subtarget.hasMips64r6() ? Mips::SCD : Mips::SCD_R6;
LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
AND = Mips::AND64;
NOR = Mips::NOR64;
ZERO = Mips::ZERO_64;