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AArch64: remove unnecessary pseudo-instruction.

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Sufficiently twisted use of TableGen lets us write patterns directly for f16
(as an i16 promoted to i32) -> f32 conversion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212933 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-07-14 11:16:02 +00:00
parent e99ebb9b2f
commit 26012cec89
3 changed files with 5 additions and 17 deletions
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13
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
View File

@ -634,19 +634,6 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
return true;
}
case AArch64::FCVTSHpseudo: {
MachineOperand Src = MI.getOperand(1);
Src.setImplicit();
unsigned SrcH =
TII->getRegisterInfo().getSubReg(Src.getReg(), AArch64::hsub);
auto MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::FCVTSHr))
.addOperand(MI.getOperand(0))
.addReg(SrcH, RegState::Undef)
.addOperand(Src);
transferImpOps(MI, MIB, MIB);
MI.eraseFromParent();
return true;
}
case AArch64::LOADgot: {
// Expand into ADRP + LDR.
unsigned DstReg = MI.getOperand(0).getReg();

5
lib/Target/AArch64/AArch64InstrInfo.td
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@ -2239,8 +2239,9 @@ def : Pat<(f32_to_f16 FPR32:$Rn),
(f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
GPR32))>;
def FCVTSHpseudo : Pseudo<(outs FPR32:$Rd), (ins FPR32:$Rn),
[(set (f32 FPR32:$Rd), (f16_to_f32 i32:$Rn))]>;
def : Pat<(f32 (f16_to_f32 i32:$Rn)),
(FCVTSHr (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS i32:$Rn, FPR32)),
hsub))>;
// When converting from f16 coming directly from a load, make sure we
// load into the FPR16 registers rather than going through the GPRs.

4
test/CodeGen/AArch64/arm64-vcvt_f.ll
View File

@ -72,8 +72,8 @@ define i16 @to_half(float %in) {
define float @from_half(i16 %in) {
; CHECK-LABEL: from_half:
; CHECK: fmov s[[HALFVAL:[0-9]+]], {{w[0-9]+}}
; CHECK: fcvt s0, h[[HALFVAL]]
; CHECK: fmov {{s[0-9]+}}, {{w[0-9]+}}
; CHECK: fcvt s0, {{h[0-9]+}}
%res = call float @llvm.convert.from.fp16(i16 %in)
ret float %res
}