diff --git a/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp b/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp
index f6034dcf4d0..c31f8c81a19 100644
--- a/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp
+++ b/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp
@@ -30,7 +30,7 @@ private:
   const TargetRegisterInfo *TRI;
   bool implicitlyDefinesSubReg(unsigned Reg, const MachineInstr *MI);
   bool processMachineBasicBlock(MachineBasicBlock *MBB);
-
+  bool usesFrameIndex(const MachineInstr *MI);
 public:
   static char ID; // Pass identification, replacement for typeid.
   explicit ARM64DeadRegisterDefinitions() : MachineFunctionPass(ID) {}
@@ -57,12 +57,27 @@ bool ARM64DeadRegisterDefinitions::implicitlyDefinesSubReg(
   return false;
 }
 
+bool ARM64DeadRegisterDefinitions::usesFrameIndex(const MachineInstr *MI) {
+  for (int I = MI->getDesc().getNumDefs(), E = MI->getNumOperands(); I != E; ++I) {
+    if (MI->getOperand(I).isFI())
+      return true;
+  }
+  return false;
+}
+
 bool
 ARM64DeadRegisterDefinitions::processMachineBasicBlock(MachineBasicBlock *MBB) {
   bool Changed = false;
   for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
        ++I) {
     MachineInstr *MI = I;
+    if (usesFrameIndex(MI)) {
+      // We need to skip this instruction because while it appears to have a
+      // dead def it uses a frame index which might expand into a multi
+      // instruction sequence during EPI
+      DEBUG(dbgs() << "    Ignoring, operand is frame index\n");
+      continue;
+    }
     for (int i = 0, e = MI->getDesc().getNumDefs(); i != e; ++i) {
       MachineOperand &MO = MI->getOperand(i);
       if (MO.isReg() && MO.isDead() && MO.isDef()) {
diff --git a/test/CodeGen/ARM64/dead-def-frame-index.ll b/test/CodeGen/ARM64/dead-def-frame-index.ll
new file mode 100644
index 00000000000..4f8cc859ee9
--- /dev/null
+++ b/test/CodeGen/ARM64/dead-def-frame-index.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=arm64 < %s | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-apple-ios7.0.0"
+
+; Function Attrs: nounwind ssp uwtable
+define i32 @test1() #0 {
+  %tmp1 = alloca i8
+  %tmp2 = alloca i32, i32 4096
+  %tmp3 = icmp eq i8* %tmp1, null
+  %tmp4 = zext i1 %tmp3 to i32
+
+  ret i32 %tmp4
+
+  ; CHECK-LABEL: test1
+  ; CHECK:   adds [[TEMP:[a-z0-9]+]], sp, #16384
+  ; CHECK:   adds [[TEMP]], [[TEMP]], #15
+}