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https://github.com/c64scene-ar/llvm-6502.git
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Implement variable-width shifts.
No testcase yet - it seems we're exposing generic codegen bugs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91221 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
04ab19cb14
commit
2625de35ed
@ -592,9 +592,21 @@ SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
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EVT VT = Op.getValueType();
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DebugLoc dl = N->getDebugLoc();
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// We currently only lower shifts of constant argument.
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// Expand non-constant shifts to loops:
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if (!isa<ConstantSDNode>(N->getOperand(1)))
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return SDValue();
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switch (Opc) {
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default:
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assert(0 && "Invalid shift opcode!");
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case ISD::SHL:
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return DAG.getNode(MSP430ISD::SHL, dl,
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VT, N->getOperand(0), N->getOperand(1));
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case ISD::SRA:
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return DAG.getNode(MSP430ISD::SRA, dl,
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VT, N->getOperand(0), N->getOperand(1));
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case ISD::SRL:
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return DAG.getNode(MSP430ISD::SRL, dl,
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VT, N->getOperand(0), N->getOperand(1));
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}
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uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
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@ -916,6 +928,8 @@ const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
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case MSP430ISD::CMP: return "MSP430ISD::CMP";
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case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
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case MSP430ISD::SHL: return "MSP430ISD::SHL";
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case MSP430ISD::SRA: return "MSP430ISD::SRA";
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}
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}
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@ -923,14 +937,132 @@ const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
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// Other Lowering Code
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//===----------------------------------------------------------------------===//
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MachineBasicBlock*
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MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
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MachineBasicBlock *BB,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
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MachineFunction *F = BB->getParent();
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MachineRegisterInfo &RI = F->getRegInfo();
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DebugLoc dl = MI->getDebugLoc();
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const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
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unsigned Opc;
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const TargetRegisterClass * RC;
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switch (MI->getOpcode()) {
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default:
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assert(0 && "Invalid shift opcode!");
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case MSP430::Shl8:
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Opc = MSP430::SHL8r1;
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RC = MSP430::GR8RegisterClass;
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break;
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case MSP430::Shl16:
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Opc = MSP430::SHL16r1;
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RC = MSP430::GR16RegisterClass;
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break;
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case MSP430::Sra8:
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Opc = MSP430::SAR8r1;
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RC = MSP430::GR8RegisterClass;
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break;
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case MSP430::Sra16:
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Opc = MSP430::SAR16r1;
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RC = MSP430::GR16RegisterClass;
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break;
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case MSP430::Srl8:
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Opc = MSP430::SAR8r1c;
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RC = MSP430::GR8RegisterClass;
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break;
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case MSP430::Srl16:
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Opc = MSP430::SAR16r1c;
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RC = MSP430::GR16RegisterClass;
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break;
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}
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator I = BB;
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++I;
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// Create loop block
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MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(I, LoopBB);
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F->insert(I, RemBB);
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// Update machine-CFG edges by transferring all successors of the current
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// block to the block containing instructions after shift.
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RemBB->transferSuccessors(BB);
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// Inform sdisel of the edge changes.
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for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
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SE = BB->succ_end(); SI != SE; ++SI)
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EM->insert(std::make_pair(*SI, RemBB));
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// Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
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BB->addSuccessor(LoopBB);
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BB->addSuccessor(RemBB);
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LoopBB->addSuccessor(RemBB);
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LoopBB->addSuccessor(LoopBB);
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unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass);
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unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass);
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unsigned ShiftReg = RI.createVirtualRegister(RC);
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unsigned ShiftReg2 = RI.createVirtualRegister(RC);
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unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
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unsigned SrcReg = MI->getOperand(1).getReg();
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unsigned DstReg = MI->getOperand(0).getReg();
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// BB:
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// cmp 0, N
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// je RemBB
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BuildMI(BB, dl, TII.get(MSP430::CMP8ir))
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.addImm(0).addReg(ShiftAmtSrcReg);
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BuildMI(BB, dl, TII.get(MSP430::JCC))
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.addMBB(RemBB)
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.addImm(MSP430CC::COND_E);
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// LoopBB:
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// ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
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// ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
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// ShiftReg2 = shift ShiftReg
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// ShiftAmt2 = ShiftAmt - 1;
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BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
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.addReg(SrcReg).addMBB(BB)
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.addReg(ShiftReg2).addMBB(LoopBB);
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BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
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.addReg(ShiftAmtSrcReg).addMBB(BB)
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.addReg(ShiftAmtReg2).addMBB(LoopBB);
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BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
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.addReg(ShiftReg);
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BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
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.addReg(ShiftAmtReg).addImm(1);
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BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
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.addMBB(LoopBB)
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.addImm(MSP430CC::COND_NE);
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// RemBB:
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// DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
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BuildMI(RemBB, dl, TII.get(MSP430::PHI), DstReg)
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.addReg(SrcReg).addMBB(BB)
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.addReg(ShiftReg2).addMBB(LoopBB);
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return RemBB;
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}
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MachineBasicBlock*
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MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
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unsigned Opc = MI->getOpcode();
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if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
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Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
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Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
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return EmitShiftInstr(MI, BB, EM);
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const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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assert((MI->getOpcode() == MSP430::Select16 ||
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MI->getOpcode() == MSP430::Select8) &&
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assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
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"Unexpected instr type to insert");
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// To "insert" a SELECT instruction, we actually have to insert the diamond
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@ -47,7 +47,7 @@ namespace llvm {
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/// CMP - Compare instruction.
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CMP,
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/// SetCC. Operand 0 is condition code, and operand 1 is the flag
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/// SetCC - Operand 0 is condition code, and operand 1 is the flag
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/// operand produced by a CMP instruction.
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SETCC,
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@ -57,9 +57,12 @@ namespace llvm {
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/// instruction.
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BR_CC,
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/// SELECT_CC. Operand 0 and operand 1 are selection variable, operand 3
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/// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
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/// is condition code and operand 4 is flag operand.
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SELECT_CC
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SELECT_CC,
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/// SHL, SRA, SRL - Non-constant shifts.
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SHL, SRA, SRL
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};
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}
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@ -99,6 +102,9 @@ namespace llvm {
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MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
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MachineBasicBlock* EmitShiftInstr(MachineInstr *MI,
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MachineBasicBlock *BB,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
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private:
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SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
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@ -31,6 +31,7 @@ def SDT_MSP430BrCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>,
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SDTCisVT<1, i8>]>;
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def SDT_MSP430SelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
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SDTCisVT<3, i8>]>;
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def SDT_MSP430Shift : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisI8<2>]>;
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//===----------------------------------------------------------------------===//
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// MSP430 Specific Node Definitions.
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@ -56,6 +57,9 @@ def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>;
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def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp, [SDNPOutFlag]>;
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def MSP430brcc : SDNode<"MSP430ISD::BR_CC", SDT_MSP430BrCC, [SDNPHasChain, SDNPInFlag]>;
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def MSP430selectcc: SDNode<"MSP430ISD::SELECT_CC", SDT_MSP430SelectCC, [SDNPInFlag]>;
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def MSP430shl : SDNode<"MSP430ISD::SHL", SDT_MSP430Shift, []>;
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def MSP430sra : SDNode<"MSP430ISD::SRA", SDT_MSP430Shift, []>;
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def MSP430srl : SDNode<"MSP430ISD::SRL", SDT_MSP430Shift, []>;
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//===----------------------------------------------------------------------===//
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// MSP430 Operand Definitions.
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@ -121,6 +125,27 @@ let usesCustomInserter = 1 in {
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"# Select16 PSEUDO",
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[(set GR16:$dst,
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(MSP430selectcc GR16:$src1, GR16:$src2, imm:$cc))]>;
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let Defs = [SRW] in {
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def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
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"# Shl8 PSEUDO",
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[(set GR8:$dst, (MSP430shl GR8:$src, GR8:$cnt))]>;
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def Shl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
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"# Shl16 PSEUDO",
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[(set GR16:$dst, (MSP430shl GR16:$src, GR8:$cnt))]>;
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def Sra8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
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"# Sra8 PSEUDO",
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[(set GR8:$dst, (MSP430sra GR8:$src, GR8:$cnt))]>;
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def Sra16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
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"# Sra16 PSEUDO",
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[(set GR16:$dst, (MSP430sra GR16:$src, GR8:$cnt))]>;
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def Srl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
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"# Srl8 PSEUDO",
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[(set GR8:$dst, (MSP430srl GR8:$src, GR8:$cnt))]>;
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def Srl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
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"# Srl16 PSEUDO",
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[(set GR16:$dst, (MSP430srl GR16:$src, GR8:$cnt))]>;
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}
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}
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let neverHasSideEffects = 1 in
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