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* Added casts to/from floating-point to integers.
* Changed // comments to #ifdef 0 to maintain syntax highlighting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6546 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -75,24 +75,27 @@ set isDeprecated = 1 in {
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}
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// Section A.5: p167
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//set op2 = 0b101 in {
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//def FBPA : F2_3<0b1000, "fbpa">; // Branch always
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//def FBPN : F2_3<0b0000, "fbpn">; // Branch never
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//def FBPU : F2_3<0b0111, "fbpu">; // Branch on unordered
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//def FBPG : F2_3<0b0110, "fbpg">; // Branch >
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//def FBPUG : F2_3<0b0101, "fbpug">; // Branch on unordered or >
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//def FBPL : F2_3<0b0100, "fbpl">; // Branch <
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//def FBPUL : F2_3<0b0011, "fbpul">; // Branch on unordered or <
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//def FBPLG : F2_3<0b0010, "fbplg">; // Branch < or >
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//def FBPNE : F2_3<0b0001, "fbpne">; // Branch !=
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//def FBPE : F2_3<0b1001, "fbpe">; // Branch ==
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//def FBPUE : F2_3<0b1010, "fbpue">; // Branch on unordered or ==
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//def FBPGE : F2_3<0b1011, "fbpge">; // Branch > or ==
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//def FBPUGE : F2_3<0b1100, "fbpuge">; // Branch unord or > or ==
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//def FBPLE : F2_3<0b1101, "fbple">; // Branch < or ==
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//def FBPULE : F2_3<0b1110, "fbpule">; // Branch unord or < or ==
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//def FBPO : F2_3<0b1111, "fbpo">; // Branch on ordered
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//}
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// Not used in the Sparc backend
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#if 0
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set op2 = 0b101 in {
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def FBPA : F2_3<0b1000, "fbpa">; // Branch always
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def FBPN : F2_3<0b0000, "fbpn">; // Branch never
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def FBPU : F2_3<0b0111, "fbpu">; // Branch on unordered
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def FBPG : F2_3<0b0110, "fbpg">; // Branch >
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def FBPUG : F2_3<0b0101, "fbpug">; // Branch on unordered or >
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def FBPL : F2_3<0b0100, "fbpl">; // Branch <
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def FBPUL : F2_3<0b0011, "fbpul">; // Branch on unordered or <
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def FBPLG : F2_3<0b0010, "fbplg">; // Branch < or >
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def FBPNE : F2_3<0b0001, "fbpne">; // Branch !=
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def FBPE : F2_3<0b1001, "fbpe">; // Branch ==
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def FBPUE : F2_3<0b1010, "fbpue">; // Branch on unordered or ==
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def FBPGE : F2_3<0b1011, "fbpge">; // Branch > or ==
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def FBPUGE : F2_3<0b1100, "fbpuge">; // Branch unord or > or ==
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def FBPLE : F2_3<0b1101, "fbple">; // Branch < or ==
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def FBPULE : F2_3<0b1110, "fbpule">; // Branch unord or < or ==
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def FBPO : F2_3<0b1111, "fbpo">; // Branch on ordered
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}
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#endif
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// Section A.6: Branch on Integer condition codes (Bicc) - p146
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set isDeprecated = 1 in {
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@ -117,26 +120,29 @@ set isDeprecated = 1 in {
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}
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// Section A.7: Branch on integer condition codes with prediction - p148
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//set op2 = 0b001 in {
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// def BPA : F2_3<0b1000, "bpa">; // Branch always
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// def BPN : F2_3<0b0000, "bpn">; // Branch never
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// def BPNE : F2_3<0b1001, "bpne">; // Branch !=
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// def BPE : F2_3<0b0001, "bpe">; // Branch ==
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// def BPG : F2_3<0b1010, "bpg">; // Branch >
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// def BPLE : F2_3<0b0010, "bple">; // Branch <=
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// def BPGE : F2_3<0b1011, "bpge">; // Branch >=
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// def BPL : F2_3<0b0011, "bpl">; // Branch <
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// def BPGU : F2_3<0b1100, "bpgu">; // Branch unsigned >
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// def BPLEU : F2_3<0b0100, "bpleu">; // Branch unsigned <=
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// def BPCC : F2_3<0b1101, "bpcc">; // Branch unsigned >=
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// def BPCS : F2_3<0b0101, "bpcs">; // Branch unsigned <=
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// def BPPOS : F2_3<0b1110, "bppos">; // Branch on positive
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// def BPNEG : F2_3<0b0110, "bpneg">; // Branch on negative
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// def BPVC : F2_3<0b1111, "bpvc">; // Branch on overflow clear
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// def BPVS : F2_3<0b0111, "bpvs">; // Branch on overflow set
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//}
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// Not used in the Sparc backend
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#if 0
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set op2 = 0b001 in {
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def BPA : F2_3<0b1000, "bpa">; // Branch always
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def BPN : F2_3<0b0000, "bpn">; // Branch never
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def BPNE : F2_3<0b1001, "bpne">; // Branch !=
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def BPE : F2_3<0b0001, "bpe">; // Branch ==
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def BPG : F2_3<0b1010, "bpg">; // Branch >
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def BPLE : F2_3<0b0010, "bple">; // Branch <=
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def BPGE : F2_3<0b1011, "bpge">; // Branch >=
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def BPL : F2_3<0b0011, "bpl">; // Branch <
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def BPGU : F2_3<0b1100, "bpgu">; // Branch unsigned >
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def BPLEU : F2_3<0b0100, "bpleu">; // Branch unsigned <=
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def BPCC : F2_3<0b1101, "bpcc">; // Branch unsigned >=
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def BPCS : F2_3<0b0101, "bpcs">; // Branch unsigned <=
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def BPPOS : F2_3<0b1110, "bppos">; // Branch on positive
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def BPNEG : F2_3<0b0110, "bpneg">; // Branch on negative
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def BPVC : F2_3<0b1111, "bpvc">; // Branch on overflow clear
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def BPVS : F2_3<0b0111, "bpvs">; // Branch on overflow set
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}
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#endif
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// Section A.8: p175 - CALL - the only Format #1 instruction
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// Section A.8: CALL - p151, the only Format #1 instruction
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def CALL : InstV9 {
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bits<30> disp;
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set op = 1;
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@ -151,22 +157,27 @@ def CALL : InstV9 {
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// Section A.10: Divide (64-bit / 32-bit) - p178
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// Not used in the Sparc backend
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//set isDeprecated = 1 in {
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//def UDIVr : F3_1<2, 0b001110, "udiv">; // udiv r, r, r
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//def UDIVi : F3_2<2, 0b001110, "udiv">; // udiv r, r, i
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//def SDIVr : F3_1<2, 0b001111, "sdiv">; // sdiv r, r, r
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//def SDIVi : F3_2<2, 0b001111, "sdiv">; // sdiv r, r, i
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//def UDIVCCr : F3_1<2, 0b011110, "udivcc">; // udivcc r, r, r
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//def UDIVCCi : F3_2<2, 0b011110, "udivcc">; // udivcc r, r, i
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//def SDIVCCr : F3_1<2, 0b011111, "sdivcc">; // sdivcc r, r, r
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//def SDIVCCi : F3_2<2, 0b011111, "sdivcc">; // sdivcc r, r, i
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//}
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#if 0
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set isDeprecated = 1 in {
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def UDIVr : F3_1<2, 0b001110, "udiv">; // udiv r, r, r
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def UDIVi : F3_2<2, 0b001110, "udiv">; // udiv r, r, i
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def SDIVr : F3_1<2, 0b001111, "sdiv">; // sdiv r, r, r
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def SDIVi : F3_2<2, 0b001111, "sdiv">; // sdiv r, r, i
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def UDIVCCr : F3_1<2, 0b011110, "udivcc">; // udivcc r, r, r
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def UDIVCCi : F3_2<2, 0b011110, "udivcc">; // udivcc r, r, i
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def SDIVCCr : F3_1<2, 0b011111, "sdivcc">; // sdivcc r, r, r
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def SDIVCCi : F3_2<2, 0b011111, "sdivcc">; // sdivcc r, r, i
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}
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#endif
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// Section A.11: DONE and RETRY - p181
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//set isPrivileged = 1 in {
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//def DONE : F3_18<0, "done">; // done
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//def RETRY : F3_18<1, "retry">; // retry
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//}
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// Not used in the Sparc backend
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#if 0
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set isPrivileged = 1 in {
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def DONE : F3_18<0, "done">; // done
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def RETRY : F3_18<1, "retry">; // retry
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}
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#endif
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// Section A.12: Floating-Point Add and Subtract - p182
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def FADDS : F3_16<2, 0b110100, 0x41, "fadds">; // fadds f, f, f
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@ -176,6 +187,41 @@ def FSUBS : F3_16<2, 0b110100, 0x45, "fsubs">; // fsubs f, f, f
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def FSUBD : F3_16<2, 0b110100, 0x46, "fsubd">; // fsubd f, f, f
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def FSUBQ : F3_16<2, 0b110100, 0x47, "fsubq">; // fsubq f, f, f
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// Section A.13: Floating-point compare - p159
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// FIXME: FCMPS, FCMPD, FCMPQ !!!
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#if 0
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def FSTOX : F3_14<2, 0b110100, 0b011001001, "fstod">; // fstod rs2, rd
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def FDTOX : F3_14<2, 0b110100, 0b011001101, "fstoq">; // fstoq rs2, rd
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def FQTOX : F3_14<2, 0b110100, 0b011000110, "fstos">; // fstos rs2, rd
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def FSTOI : F3_14<2, 0b110100, 0b011001110, "fdtoq">; // fdtoq rs2, rd
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def FDTOI : F3_14<2, 0b110100, 0b011000111, "fqtos">; // fqtos rs2, rd
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def FQTOI : F3_14<2, 0b110100, 0b011001011, "fqtod">; // fqtod rs2, rd
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#endif
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// Section A.14: Convert floating-point to integer - p161
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def FSTOX : F3_14<2, 0b110100, 0b010000001, "fstox">; // fstox rs2, rd
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def FDTOX : F3_14<2, 0b110100, 0b010000010, "fstox">; // fstox rs2, rd
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def FQTOX : F3_14<2, 0b110100, 0b010000011, "fstox">; // fstox rs2, rd
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def FSTOI : F3_14<2, 0b110100, 0b011010001, "fstoi">; // fstoi rs2, rd
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def FDTOI : F3_14<2, 0b110100, 0b011010010, "fdtoi">; // fdtoi rs2, rd
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def FQTOI : F3_14<2, 0b110100, 0b011010011, "fqtoi">; // fqtoi rs2, rd
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// Section A.15: Convert between floating-point formats - p162
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def FSTOD : F3_14<2, 0b110100, 0b011001001, "fstod">; // fstod rs2, rd
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def FSTOQ : F3_14<2, 0b110100, 0b011001101, "fstoq">; // fstoq rs2, rd
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def FDTOS : F3_14<2, 0b110100, 0b011000110, "fstos">; // fstos rs2, rd
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def FDTOQ : F3_14<2, 0b110100, 0b011001110, "fdtoq">; // fdtoq rs2, rd
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def FQTOS : F3_14<2, 0b110100, 0b011000111, "fqtos">; // fqtos rs2, rd
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def FQTOD : F3_14<2, 0b110100, 0b011001011, "fqtod">; // fqtod rs2, rd
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// Section A.16: Convert integer to floating-point - p163
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def FXTOS : F3_14<2, 0b110100, 0b010000100, "fxtos">; // fxtos rs2, rd
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def FXTOD : F3_14<2, 0b110100, 0b010001000, "fxtod">; // fxtod rs2, rd
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def FXTOQ : F3_14<2, 0b110100, 0b010001100, "fxtoq">; // fxtoq rs2, rd
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def FITOS : F3_14<2, 0b110100, 0b011000100, "fitos">; // fitos rs2, rd
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def FITOD : F3_14<2, 0b110100, 0b011001000, "fitod">; // fitod rs2, rd
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def FITOQ : F3_14<2, 0b110100, 0b011001100, "fitoq">; // fitoq rs2, rd
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// Section A.17: Floating-Point Move - p164
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def FMOVS : F3_14<2, 0b110100, 0b000000001, "fmovs">; // fmovs r, r
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def FMOVD : F3_14<2, 0b110100, 0b000000010, "fmovs">; // fmovd r, r
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@ -218,9 +264,6 @@ def JMPLCALLi : F3_2<2, 0b111000, "jmpl">; // jmpl [r+i], r
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def JMPLRETr : F3_1<2, 0b111000, "jmpl">; // jmpl [r+r], r
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def JMPLRETi : F3_2<2, 0b111000, "jmpl">; // jmpl [r+i], r
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// FIXME: FCMPS, FCMPD, FCMPQ !!!
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// FIXME: FMULS, FMULD, FMULQ, ...
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// Section A.25: Load Floating-Point - p173
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def LDFr : F3_1<3, 0b100000, "ld">; // ld [r+r], r
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def LDFi : F3_2<3, 0b100000, "ld">; // ld [r+i], r
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@ -256,10 +299,12 @@ def LDUWi : F3_2<3, 0b000000, "lduw">; // lduw [r+i], r
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// LDD should no longer be used, LDX should be used instead
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def LDXr : F3_1<3, 0b001011, "ldx">; // ldx [r+r], r
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def LDXi : F3_2<3, 0b001011, "ldx">; // ldx [r+i], r
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//set isDeprecated = 1 in {
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// def LDDr : F3_1<3, 0b000011, "ldd">; // ldd [r+r], r
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// def LDDi : F3_2<3, 0b000011, "ldd">; // ldd [r+i], r
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//}
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#if 0
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set isDeprecated = 1 in {
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def LDDr : F3_1<3, 0b000011, "ldd">; // ldd [r+r], r
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def LDDi : F3_2<3, 0b000011, "ldd">; // ldd [r+i], r
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}
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#endif
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// Section A.31: Logical operations
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def ANDr : F3_1<2, 0b000001, "and">; // and r, r, r
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@ -289,6 +334,9 @@ def XNORi : F3_2<2, 0b000111, "xnor">; // xnor r, r, i
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def XNORccr : F3_1<2, 0b010111, "xnorcc">; // xnorcc r, r, r
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def XNORcci : F3_2<2, 0b010111, "xnorcc">; // xnorcc r, r, i
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// Section A.32: Memory Barrier - p186
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// Not currently used in the Sparc backend
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#if 0
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// Section A.33: Move Floating-Point Register on Condition (FMOVcc)
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// For integer condition codes
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@ -331,8 +379,44 @@ def FMOVFO : F4_7<2, 0b110101, 0b1111, "fmovfo">; // fmovfo r, r
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// FIXME: Section A.34: Move F-P Register on Integer Register (FMOVr)
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// FIXME: Section A.35: Move Integer Register on Condition (MOVcc)
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// Section A.35: Move Integer Register on Condition (MOVcc) - p194
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// For integer condition codes
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#if 0
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def MOVA :
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def MOVN :
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def MOVNE :
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def MOVE :
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def MOVG :
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def MOVLE :
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def MOVGE :
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def MOVL :
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def MOVGU :
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def MOVLEU :
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def MOVCC :
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def MOVCS :
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def MOVPOS :
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def MOVNEG :
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def MOVVC :
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def MOVVS :
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// For floating-point condition codes
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def MOVFA :
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def MOVFN :
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def MOVFU :
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def MOVFG :
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def MOVFUG :
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def MOVFL :
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def MOVFUL :
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def MOVFLG :
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def MOVFNE :
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def MOVFE :
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def MOVFUE :
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def MOVFGE :
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def MOVFUGE :
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def MOVFLE :
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def MOVFULE :
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def MOVFO :
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#endif
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// FIXME: Section A.36: Move Integer Register on Register Condition (MOVR)
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@ -346,19 +430,21 @@ def SDIVXi : F3_2<2, 0b101101, "sdivx">; // mulx r, i, r
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def UDIVXi : F3_2<2, 0b001101, "udivx">; // mulx r, i, r
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// Section A.38: Multiply (32-bit) - p200
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// Not used in the Sparc backend?
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//set Inst{13} = 0 in {
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// def UMULr : F3_1<2, 0b001010, "umul">; // umul r, r, r
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// def SMULr : F3_1<2, 0b001011, "smul">; // smul r, r, r
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// def UMULCCr : F3_1<2, 0b011010, "umulcc">; // mulcc r, r, r
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// def SMULCCr : F3_1<2, 0b011011, "smulcc">; // smulcc r, r, r
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//}
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//set Inst{13} = 1 in {
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// def UMULi : F3_1<2, 0b001010, "umul">; // umul r, i, r
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// def SMULi : F3_1<2, 0b001011, "smul">; // smul r, i, r
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// def UMULCCi : F3_1<2, 0b011010, "umulcc">; // umulcc r, i, r
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// def SMULCCi : F3_1<2, 0b011011, "smulcc">; // smulcc r, i, r
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//}
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// Not used in the Sparc backend
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#if 0
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set Inst{13} = 0 in {
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def UMULr : F3_1<2, 0b001010, "umul">; // umul r, r, r
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def SMULr : F3_1<2, 0b001011, "smul">; // smul r, r, r
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def UMULCCr : F3_1<2, 0b011010, "umulcc">; // mulcc r, r, r
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def SMULCCr : F3_1<2, 0b011011, "smulcc">; // smulcc r, r, r
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}
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set Inst{13} = 1 in {
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def UMULi : F3_1<2, 0b001010, "umul">; // umul r, i, r
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def SMULi : F3_1<2, 0b001011, "smul">; // smul r, i, r
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def UMULCCi : F3_1<2, 0b011010, "umulcc">; // umulcc r, i, r
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def SMULCCi : F3_1<2, 0b011011, "smulcc">; // smulcc r, i, r
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}
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#endif
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// Section A.39: FIXME
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@ -403,15 +489,19 @@ set op2 = 0b100 in {
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}
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// Section A.49: Shift - p221
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// uses 5 least significant bits of rs2
|
||||
//set x = 0 in {
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||||
// def SLLr5 : F3_11<2, 0b100101, "sll">; // sll r, r, r
|
||||
// def SRLr5 : F3_11<2, 0b100110, "srl">; // srl r, r, r
|
||||
// def SRAr5 : F3_11<2, 0b100111, "sra">; // sra r, r, r
|
||||
// def SLLXr5 : F3_11<2, 0b100101, "sllx">; // sllx r, r, r
|
||||
// def SRLXr5 : F3_11<2, 0b100110, "srlx">; // srlx r, r, r
|
||||
// def SRAXr5 : F3_11<2, 0b100111, "srax">; // srax r, r, r
|
||||
//}
|
||||
// Not currently used in the Sparc backend
|
||||
#if 0
|
||||
uses 5 least significant bits of rs2
|
||||
set x = 0 in {
|
||||
def SLLr5 : F3_11<2, 0b100101, "sll">; // sll r, r, r
|
||||
def SRLr5 : F3_11<2, 0b100110, "srl">; // srl r, r, r
|
||||
def SRAr5 : F3_11<2, 0b100111, "sra">; // sra r, r, r
|
||||
def SLLXr5 : F3_11<2, 0b100101, "sllx">; // sllx r, r, r
|
||||
def SRLXr5 : F3_11<2, 0b100110, "srlx">; // srlx r, r, r
|
||||
def SRAXr5 : F3_11<2, 0b100111, "srax">; // srax r, r, r
|
||||
}
|
||||
#endif
|
||||
|
||||
// uses 6 least significant bits of rs2
|
||||
set x = 1 in {
|
||||
def SLLr6 : F3_11<2, 0b100101, "sll">; // sll r, r, r
|
||||
@ -422,12 +512,15 @@ set x = 1 in {
|
||||
def SRAXr6 : F3_11<2, 0b100111, "srax">; // srax r, r, r
|
||||
}
|
||||
|
||||
//def SLLi5 : F3_12<2, 0b100101, "sll">; // sll r, shcnt32, r
|
||||
//def SRLi5 : F3_12<2, 0b100110, "srl">; // srl r, shcnt32, r
|
||||
//def SRAi5 : F3_12<2, 0b100111, "sra">; // sra r, shcnt32, r
|
||||
//def SLLXi5 : F3_12<2, 0b100101, "sllx">; // sllx r, shcnt32, r
|
||||
//def SRLXi5 : F3_12<2, 0b100110, "srlx">; // srlx r, shcnt32, r
|
||||
//def SRAXi5 : F3_12<2, 0b100111, "srax">; // srax r, shcnt32, r
|
||||
// Not currently used in the Sparc backend
|
||||
#if 0
|
||||
def SLLi5 : F3_12<2, 0b100101, "sll">; // sll r, shcnt32, r
|
||||
def SRLi5 : F3_12<2, 0b100110, "srl">; // srl r, shcnt32, r
|
||||
def SRAi5 : F3_12<2, 0b100111, "sra">; // sra r, shcnt32, r
|
||||
def SLLXi5 : F3_12<2, 0b100101, "sllx">; // sllx r, shcnt32, r
|
||||
def SRLXi5 : F3_12<2, 0b100110, "srlx">; // srlx r, shcnt32, r
|
||||
def SRAXi5 : F3_12<2, 0b100111, "srax">; // srax r, shcnt32, r
|
||||
#endif
|
||||
|
||||
def SLLi6 : F3_13<2, 0b100101, "sll">; // sll r, shcnt64, r
|
||||
def SRLi6 : F3_13<2, 0b100110, "srl">; // srl r, shcnt64, r
|
||||
@ -445,9 +538,13 @@ def STFr : F3_1<3, 0b100100, "st">; // st r, [r+r]
|
||||
def STFi : F3_2<3, 0b100100, "st">; // st r, [r+i]
|
||||
def STDFr : F3_1<3, 0b100111, "std">; // std r, [r+r]
|
||||
def STDFi : F3_2<3, 0b100111, "std">; // std r, [r+i]
|
||||
|
||||
// Not currently used in the Sparc backend
|
||||
//def STQFr : F3_1<3, 0b100110, "stq">; // stq r, [r+r]
|
||||
//def STQFi : F3_2<3, 0b100110, "stq">; // stq r, [r+i]
|
||||
#if 0
|
||||
def STQFr : F3_1<3, 0b100110, "stq">; // stq r, [r+r]
|
||||
def STQFi : F3_2<3, 0b100110, "stq">; // stq r, [r+i]
|
||||
#endif
|
||||
|
||||
set isDeprecated = 1 in {
|
||||
def STFSRr : F3_1<3, 0b100101, "st">; // st r, [r+r]
|
||||
def STFSRi : F3_2<3, 0b100101, "st">; // st r, [r+i]
|
||||
|
Loading…
Reference in New Issue
Block a user