diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h
index f673c99dbeb..47d33abbf7f 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -116,8 +116,10 @@ namespace ARMII {
     // Thumb format
     ThumbFrm      = 24 << FormShift,
 
+    // Miscelleaneous format
+    MiscFrm       = 25 << FormShift,
+
     // NEON formats
-    NEONFrm       = 25 << FormShift,
     NEONGetLnFrm  = 26 << FormShift,
     NEONSetLnFrm  = 27 << FormShift,
     NEONDupFrm    = 28 << FormShift,
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index d487df16df5..6328716a232 100644
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -50,15 +50,11 @@ def VFPLdStMulFrm : Format<22>;
 def VFPMiscFrm    : Format<23>;
 
 def ThumbFrm      : Format<24>;
+def MiscFrm       : Format<25>;
 
-def NEONFrm       : Format<25>;
 def NEONGetLnFrm  : Format<26>;
 def NEONSetLnFrm  : Format<27>;
 def NEONDupFrm    : Format<28>;
-
-def MiscFrm       : Format<29>;
-def ThumbMiscFrm  : Format<30>;
-
 def NLdStFrm       : Format<31>;
 def N1RegModImmFrm : Format<32>;
 def N2RegFrm       : Format<33>;
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index 669cf54678f..36b9cad514b 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -2839,12 +2839,6 @@ static bool DisassembleNVTBLFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
   return true;
 }
 
-static bool DisassembleNEONFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
-    unsigned short NumOps, unsigned &NumOpsAdded, BO) {
-  assert(0 && "Unreachable code!");
-  return false;
-}
-
 // Vector Get Lane (move scalar to ARM core register) Instructions.
 // VGETLNi32, VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8: Rt Dn index
 static bool DisassembleNEONGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
@@ -3060,13 +3054,6 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
   return false;
 }
 
-static bool DisassembleThumbMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
-    unsigned short NumOps, unsigned &NumOpsAdded, BO) {
-
-  assert(0 && "Unexpected thumb misc. instruction!");
-  return false;
-}
-
 /// FuncPtrs - FuncPtrs maps ARMFormat to its corresponding DisassembleFP.
 /// We divide the disassembly task into different categories, with each one
 /// corresponding to a specific instruction encoding format.  There could be
@@ -3098,12 +3085,12 @@ static const DisassembleFP FuncPtrs[] = {
   &DisassembleVFPLdStMulFrm,
   &DisassembleVFPMiscFrm,
   &DisassembleThumbFrm,
-  &DisassembleNEONFrm,
+  &DisassembleMiscFrm,
   &DisassembleNEONGetLnFrm,
   &DisassembleNEONSetLnFrm,
   &DisassembleNEONDupFrm,
-  &DisassembleMiscFrm,
-  &DisassembleThumbMiscFrm,
+  0,
+  0,
 
   // VLD and VST (including one lane) Instructions.
   &DisassembleNLdSt,