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I'm introducing a new machine model to simultaneously allow simple

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subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
2012-07-07 04:00:00 +00:00
parent 06495cd7f2
commit 2661b411cc
27 changed files with 905 additions and 503 deletions
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12
utils/TableGen/CodeGenTarget.cpp
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@ -16,6 +16,7 @@
#include "CodeGenTarget.h"
#include "CodeGenIntrinsics.h"
#include "CodeGenSchedule.h"
#include "llvm/TableGen/Record.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/STLExtras.h"
@ -112,7 +113,7 @@ std::string llvm::getQualifiedName(const Record *R) {
/// getTarget - Return the current instance of the Target class.
///
CodeGenTarget::CodeGenTarget(RecordKeeper &records)
: Records(records), RegBank(0) {
: Records(records), RegBank(0), SchedModels(0) {
std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
if (Targets.size() == 0)
throw std::string("ERROR: No 'Target' subclasses defined!");
@ -121,6 +122,10 @@ CodeGenTarget::CodeGenTarget(RecordKeeper &records)
TargetRec = Targets[0];
}
CodeGenTarget::~CodeGenTarget() {
delete RegBank;
delete SchedModels;
}
const std::string &CodeGenTarget::getName() const {
return TargetRec->getName();
@ -235,6 +240,11 @@ void CodeGenTarget::ReadLegalValueTypes() const {
LegalValueTypes.end());
}
CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
if (!SchedModels)
SchedModels = new CodeGenSchedModels(Records, *this);
return *SchedModels;
}
void CodeGenTarget::ReadInstructions() const {
std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");