From 268e96a8a61cecfc7000e300b8e39e9e15ce756b Mon Sep 17 00:00:00 2001 From: Nico Rieck Date: Sun, 16 Feb 2014 07:31:05 +0000 Subject: [PATCH] Fix broken CHECK lines git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201479 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/Analysis/CostModel/ARM/cast.ll | 2 +- test/CodeGen/AArch64/fcvt-int.ll | 2 +- test/CodeGen/ARM/2011-10-26-memset-inline.ll | 8 ++++---- test/CodeGen/ARM/build-attributes.ll | 6 +++--- test/CodeGen/ARM/constantfp.ll | 12 ++++++------ test/CodeGen/ARM/debug-frame-large-stack.ll | 8 ++++---- test/CodeGen/Hexagon/packetize_cond_inst.ll | 2 +- test/CodeGen/X86/2011-05-09-loaduse.ll | 2 +- test/CodeGen/X86/tbm-intrinsics-x86_64.ll | 2 +- test/CodeGen/X86/vector-gep.ll | 2 +- test/MC/ELF/local-reloc.s | 2 +- test/Transforms/DeadArgElim/deadexternal.ll | 2 +- 12 files changed, 25 insertions(+), 25 deletions(-) diff --git a/test/Analysis/CostModel/ARM/cast.ll b/test/Analysis/CostModel/ARM/cast.ll index 0cdd61cac4f..a6ed798b95b 100644 --- a/test/Analysis/CostModel/ARM/cast.ll +++ b/test/Analysis/CostModel/ARM/cast.ll @@ -528,7 +528,7 @@ define i32 @casts() { %r242 = uitofp <16 x i8> undef to <16 x double> ; CHECK: cost of 64 {{.*}} sitofp %r243 = sitofp <16 x i8> undef to <16 x double> - ; C4ECK: cost of 64 {{.*}} uitofp + ; CHECK: cost of 64 {{.*}} uitofp %r244 = uitofp <16 x i16> undef to <16 x double> ; CHECK: cost of 64 {{.*}} sitofp %r245 = sitofp <16 x i16> undef to <16 x double> diff --git a/test/CodeGen/AArch64/fcvt-int.ll b/test/CodeGen/AArch64/fcvt-int.ll index b28eb3ea1be..97427a75c91 100644 --- a/test/CodeGen/AArch64/fcvt-int.ll +++ b/test/CodeGen/AArch64/fcvt-int.ll @@ -69,7 +69,7 @@ define float @test_i32tofloat(i32 %in) { ; CHECK-DAG: scvtf [[SIG:s[0-9]+]], {{w[0-9]+}} %res = fsub float %signed, %unsigned -; CHECL: fsub {{s[0-9]+}}, [[SIG]], [[UNSIG]] +; CHECK: fsub {{s[0-9]+}}, [[SIG]], [[UNSIG]] ret float %res ; CHECK: ret } diff --git a/test/CodeGen/ARM/2011-10-26-memset-inline.ll b/test/CodeGen/ARM/2011-10-26-memset-inline.ll index 03614eddbf7..17bd291a6b5 100644 --- a/test/CodeGen/ARM/2011-10-26-memset-inline.ll +++ b/test/CodeGen/ARM/2011-10-26-memset-inline.ll @@ -6,10 +6,10 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64- target triple = "thumbv7-apple-ios5.0.0" ; CHECK-GENERIC: strb -; CHECK-GENERIT-NEXT: strb -; CHECK-GENERIT-NEXT: strb -; CHECK-GENERIT-NEXT: strb -; CHECK-GENERIT-NEXT: strb +; CHECK-GENERIC-NEXT: strb +; CHECK-GENERIC-NEXT: strb +; CHECK-GENERIC-NEXT: strb +; CHECK-GENERIC-NEXT: strb ; CHECK-UNALIGNED: strb ; CHECK-UNALIGNED: str define void @foo(i8* nocapture %c) nounwind optsize { diff --git a/test/CodeGen/ARM/build-attributes.ll b/test/CodeGen/ARM/build-attributes.ll index 013138b3c20..3e825e8d7d6 100644 --- a/test/CodeGen/ARM/build-attributes.ll +++ b/test/CodeGen/ARM/build-attributes.ll @@ -283,8 +283,8 @@ ; CORTEX-A9-MP: .eabi_attribute 23, 3 ; CORTEX-A9-MP: .eabi_attribute 24, 1 ; CORTEX-A9-MP: .eabi_attribute 25, 1 -; CORTEX-A9-NOT: .eabi_attribute 27 -; CORTEX-A9-NOT: .eabi_attribute 28 +; CORTEX-A9-MP-NOT: .eabi_attribute 27 +; CORTEX-A9-MP-NOT: .eabi_attribute 28 ; CORTEX-A9-MP: .eabi_attribute 36, 1 ; CORTEX-A9-MP: .eabi_attribute 42, 1 ; CORTEX-A9-MP: .eabi_attribute 68, 1 @@ -401,7 +401,7 @@ ; CORTEX-M4-HARD: .eabi_attribute 36, 1 ; CORTEX-M4-HARD-NOT: .eabi_attribute 42 ; CORTEX-M4-HARD-NOT: .eabi_attribute 44 -; CORTEX-M4-HRAD-NOT: .eabi_attribute 68 +; CORTEX-M4-HARD-NOT: .eabi_attribute 68 ; CORTEX-R5: .cpu cortex-r5 ; CORTEX-R5: .eabi_attribute 6, 10 diff --git a/test/CodeGen/ARM/constantfp.ll b/test/CodeGen/ARM/constantfp.ll index 974bdd729ef..27b6e9b904d 100644 --- a/test/CodeGen/ARM/constantfp.ll +++ b/test/CodeGen/ARM/constantfp.ll @@ -15,7 +15,7 @@ define arm_aapcs_vfpcc float @test_vmov_imm() { ; CHECK: vmov.i32 d0, #0 ; CHECK-NONEON-LABEL: test_vmov_imm: -; CHECK_NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} +; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} ret float 0.0 } @@ -24,7 +24,7 @@ define arm_aapcs_vfpcc float @test_vmvn_imm() { ; CHECK: vmvn.i32 d0, #0xb0000000 ; CHECK-NONEON-LABEL: test_vmvn_imm: -; CHECK_NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} +; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} ret float 8589934080.0 } @@ -33,7 +33,7 @@ define arm_aapcs_vfpcc double @test_vmov_f64() { ; CHECK: vmov.f64 d0, #1.0 ; CHECK-NONEON-LABEL: test_vmov_f64: -; CHECK_NONEON: vmov.f64 d0, #1.0 +; CHECK-NONEON: vmov.f64 d0, #1.0 ret double 1.0 } @@ -43,7 +43,7 @@ define arm_aapcs_vfpcc double @test_vmov_double_imm() { ; CHECK: vmov.i32 d0, #0 ; CHECK-NONEON-LABEL: test_vmov_double_imm: -; CHECK_NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} +; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} ret double 0.0 } @@ -52,7 +52,7 @@ define arm_aapcs_vfpcc double @test_vmvn_double_imm() { ; CHECK: vmvn.i32 d0, #0xb0000000 ; CHECK-NONEON-LABEL: test_vmvn_double_imm: -; CHECK_NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} +; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} ret double 0x4fffffff4fffffff } @@ -63,6 +63,6 @@ define arm_aapcs_vfpcc double @test_notvmvn_double_imm() { ; CHECK: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} ; CHECK-NONEON-LABEL: test_notvmvn_double_imm: -; CHECK_NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} +; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} ret double 0x4fffffffffffffff } diff --git a/test/CodeGen/ARM/debug-frame-large-stack.ll b/test/CodeGen/ARM/debug-frame-large-stack.ll index e1fc029a952..5bafce9407e 100644 --- a/test/CodeGen/ARM/debug-frame-large-stack.ll +++ b/test/CodeGen/ARM/debug-frame-large-stack.ll @@ -28,10 +28,10 @@ define void @test1() { ; CHECK-ARM: sub sp, sp, #256 ; CHECK-ARM: .cfi_endproc -; CHECK-ARM-FP_ELIM-LABEL: test1: -; CHECK-ARM-FP_ELIM: .cfi_startproc -; CHECK-ARM-FP_ELIM: sub sp, sp, #256 -; CHECK-ARM-FP_ELIM: .cfi_endproc +; CHECK-ARM-FP-ELIM-LABEL: test1: +; CHECK-ARM-FP-ELIM: .cfi_startproc +; CHECK-ARM-FP-ELIM: sub sp, sp, #256 +; CHECK-ARM-FP-ELIM: .cfi_endproc define void @test2() { %tmp = alloca [ 4168 x i8 ] , align 4 diff --git a/test/CodeGen/Hexagon/packetize_cond_inst.ll b/test/CodeGen/Hexagon/packetize_cond_inst.ll index a48a9f62ec6..1fc6e82959e 100644 --- a/test/CodeGen/Hexagon/packetize_cond_inst.ll +++ b/test/CodeGen/Hexagon/packetize_cond_inst.ll @@ -12,7 +12,7 @@ target triple = "hexagon-unknown--elf" ; } ; CHECK: cmp ; CHECK-NEXT: add -; CHECH-NEXT: add +; CHECK-NEXT: add define i32 @ifcnv_add(i32, i32, i32) nounwind readnone { %4 = icmp sgt i32 %2, %1 br i1 %4, label %5, label %7 diff --git a/test/CodeGen/X86/2011-05-09-loaduse.ll b/test/CodeGen/X86/2011-05-09-loaduse.ll index adcea5cf615..c772e4c7f4e 100644 --- a/test/CodeGen/X86/2011-05-09-loaduse.ll +++ b/test/CodeGen/X86/2011-05-09-loaduse.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s ;CHECK-LABEL: test: -;CHECK-not: pshufd +;CHECK-NOT: pshufd ;CHECK: ret define float @test(<4 x float>* %A) nounwind { entry: diff --git a/test/CodeGen/X86/tbm-intrinsics-x86_64.ll b/test/CodeGen/X86/tbm-intrinsics-x86_64.ll index 1bc617541ed..1beee72dfd0 100644 --- a/test/CodeGen/X86/tbm-intrinsics-x86_64.ll +++ b/test/CodeGen/X86/tbm-intrinsics-x86_64.ll @@ -34,7 +34,7 @@ declare i64 @llvm.x86.tbm.bextri.u64(i64, i64) nounwind readnone define i64 @test_x86_tbm_bextri_u64_m(i64* nocapture %a) nounwind readonly { entry: - ; CHECK-LABEl: test_x86_tbm_bextri_u64_m: + ; CHECK-LABEL: test_x86_tbm_bextri_u64_m: ; CHECK-NOT: mov ; CHECK: bextr $ %tmp1 = load i64* %a, align 8 diff --git a/test/CodeGen/X86/vector-gep.ll b/test/CodeGen/X86/vector-gep.ll index 762c8a81286..9c68f44dffb 100644 --- a/test/CodeGen/X86/vector-gep.ll +++ b/test/CodeGen/X86/vector-gep.ll @@ -34,7 +34,7 @@ entry: ;CHECK-LABEL: AGEP2: define i32 @AGEP2(<4 x i32*> %param, <4 x i32> %off) nounwind { entry: -;CHECK_LABEL: AGEP2 +;CHECK-LABEL: AGEP2 ;CHECK: vpslld $2 ;CHECK-NEXT: vpadd %A2 = getelementptr <4 x i32*> %param, <4 x i32> %off diff --git a/test/MC/ELF/local-reloc.s b/test/MC/ELF/local-reloc.s index 0c745197c81..19b95098668 100644 --- a/test/MC/ELF/local-reloc.s +++ b/test/MC/ELF/local-reloc.s @@ -6,7 +6,7 @@ movl foo, %r14d foo: -// CHECKT: Relocations [ +// CHECK: Relocations [ // CHECK: Section (2) .rela.text { // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32S .text 0x{{[^ ]+}} // CHECK-NEXT: } diff --git a/test/Transforms/DeadArgElim/deadexternal.ll b/test/Transforms/DeadArgElim/deadexternal.ll index acbcf75ee49..665d7dbf493 100644 --- a/test/Transforms/DeadArgElim/deadexternal.ll +++ b/test/Transforms/DeadArgElim/deadexternal.ll @@ -32,7 +32,7 @@ entry: %i = alloca i32, align 4 store volatile i32 10, i32* %i, align 4 ; CHECK: %tmp = load volatile i32* %i, align 4 -; CHECK-next: call void @f(i32 undef) +; CHECK-NEXT: call void @f(i32 undef) %tmp = load volatile i32* %i, align 4 call void @f(i32 %tmp) ret void