mirror of
https://github.com/c64scene-ar/llvm-6502.git
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R600: Emit native instructions for tex
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178452 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune
parent
79f615cbfe
commit
2691fe98a7
@ -66,8 +66,6 @@ private:
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void EmitSrcISA(const MCInst &MI, unsigned RegOpIdx, unsigned SelOpIdx,
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raw_ostream &OS) const;
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void EmitDst(const MCInst &MI, raw_ostream &OS) const;
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void EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
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raw_ostream &OS) const;
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void EmitFCInstr(const MCInst &MI, raw_ostream &OS) const;
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void EmitNullBytes(unsigned int byteCount, raw_ostream &OS) const;
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@ -140,9 +138,7 @@ MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
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void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (isTexOp(MI.getOpcode())) {
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EmitTexInstr(MI, Fixups, OS);
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} else if (isFCOp(MI.getOpcode())){
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if (isFCOp(MI.getOpcode())){
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EmitFCInstr(MI, OS);
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} else if (MI.getOpcode() == AMDGPU::RETURN ||
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MI.getOpcode() == AMDGPU::BUNDLE ||
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@ -175,6 +171,77 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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Emit(InstWord2, OS);
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break;
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}
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case AMDGPU::TEX_LD:
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case AMDGPU::TEX_GET_TEXTURE_RESINFO:
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case AMDGPU::TEX_SAMPLE:
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case AMDGPU::TEX_SAMPLE_C:
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case AMDGPU::TEX_SAMPLE_L:
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case AMDGPU::TEX_SAMPLE_C_L:
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case AMDGPU::TEX_SAMPLE_LB:
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case AMDGPU::TEX_SAMPLE_C_LB:
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case AMDGPU::TEX_SAMPLE_G:
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case AMDGPU::TEX_SAMPLE_C_G:
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case AMDGPU::TEX_GET_GRADIENTS_H:
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case AMDGPU::TEX_GET_GRADIENTS_V:
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case AMDGPU::TEX_SET_GRADIENTS_H:
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case AMDGPU::TEX_SET_GRADIENTS_V: {
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unsigned Opcode = MI.getOpcode();
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bool HasOffsets = (Opcode == AMDGPU::TEX_LD);
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unsigned OpOffset = HasOffsets ? 3 : 0;
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int64_t Sampler = MI.getOperand(OpOffset + 3).getImm();
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int64_t TextureType = MI.getOperand(OpOffset + 4).getImm();
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uint32_t SrcSelect[4] = {0, 1, 2, 3};
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uint32_t Offsets[3] = {0, 0, 0};
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uint64_t CoordType[4] = {1, 1, 1, 1};
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if (HasOffsets)
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for (unsigned i = 0; i < 3; i++)
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Offsets[i] = MI.getOperand(i + 2).getImm();
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if (TextureType == TEXTURE_RECT ||
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TextureType == TEXTURE_SHADOWRECT) {
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CoordType[ELEMENT_X] = 0;
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CoordType[ELEMENT_Y] = 0;
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}
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if (TextureType == TEXTURE_1D_ARRAY ||
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TextureType == TEXTURE_SHADOW1D_ARRAY) {
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if (Opcode == AMDGPU::TEX_SAMPLE_C_L ||
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Opcode == AMDGPU::TEX_SAMPLE_C_LB) {
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CoordType[ELEMENT_Y] = 0;
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} else {
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CoordType[ELEMENT_Z] = 0;
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SrcSelect[ELEMENT_Z] = ELEMENT_Y;
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}
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} else if (TextureType == TEXTURE_2D_ARRAY ||
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TextureType == TEXTURE_SHADOW2D_ARRAY) {
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CoordType[ELEMENT_Z] = 0;
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}
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if ((TextureType == TEXTURE_SHADOW1D ||
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TextureType == TEXTURE_SHADOW2D ||
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TextureType == TEXTURE_SHADOWRECT ||
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TextureType == TEXTURE_SHADOW1D_ARRAY) &&
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Opcode != AMDGPU::TEX_SAMPLE_C_L &&
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Opcode != AMDGPU::TEX_SAMPLE_C_LB) {
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SrcSelect[ELEMENT_W] = ELEMENT_Z;
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}
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uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups) |
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CoordType[ELEMENT_X] << 60 | CoordType[ELEMENT_Y] << 61 |
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CoordType[ELEMENT_Z] << 62 | CoordType[ELEMENT_W] << 63;
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uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 |
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SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 |
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SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
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Offsets[2] << 10;
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EmitByte(INSTR_TEX, OS);
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Emit(Word01, OS);
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Emit(Word2, OS);
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break;
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}
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case AMDGPU::EG_ExportSwz:
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case AMDGPU::R600_ExportSwz:
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case AMDGPU::EG_ExportBuf:
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@ -334,99 +401,6 @@ void R600MCCodeEmitter::EmitSrcISA(const MCInst &MI, unsigned RegOpIdx,
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Emit(InlineConstant.i, OS);
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}
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void R600MCCodeEmitter::EmitTexInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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raw_ostream &OS) const {
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unsigned Opcode = MI.getOpcode();
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bool hasOffsets = (Opcode == AMDGPU::TEX_LD);
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unsigned OpOffset = hasOffsets ? 3 : 0;
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int64_t Resource = MI.getOperand(OpOffset + 2).getImm();
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int64_t Sampler = MI.getOperand(OpOffset + 3).getImm();
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int64_t TextureType = MI.getOperand(OpOffset + 4).getImm();
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unsigned srcSelect[4] = {0, 1, 2, 3};
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// Emit instruction type
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EmitByte(1, OS);
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// Emit instruction
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EmitByte(getBinaryCodeForInstr(MI, Fixups), OS);
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// Emit resource id
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EmitByte(Resource, OS);
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// Emit source register
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EmitByte(getHWReg(MI.getOperand(1).getReg()), OS);
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// XXX: Emit src isRelativeAddress
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EmitByte(0, OS);
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// Emit destination register
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EmitByte(getHWReg(MI.getOperand(0).getReg()), OS);
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// XXX: Emit dst isRealtiveAddress
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EmitByte(0, OS);
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// XXX: Emit dst select
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EmitByte(0, OS); // X
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EmitByte(1, OS); // Y
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EmitByte(2, OS); // Z
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EmitByte(3, OS); // W
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// XXX: Emit lod bias
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EmitByte(0, OS);
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// XXX: Emit coord types
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unsigned coordType[4] = {1, 1, 1, 1};
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if (TextureType == TEXTURE_RECT
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|| TextureType == TEXTURE_SHADOWRECT) {
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coordType[ELEMENT_X] = 0;
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coordType[ELEMENT_Y] = 0;
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}
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if (TextureType == TEXTURE_1D_ARRAY
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|| TextureType == TEXTURE_SHADOW1D_ARRAY) {
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if (Opcode == AMDGPU::TEX_SAMPLE_C_L || Opcode == AMDGPU::TEX_SAMPLE_C_LB) {
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coordType[ELEMENT_Y] = 0;
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} else {
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coordType[ELEMENT_Z] = 0;
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srcSelect[ELEMENT_Z] = ELEMENT_Y;
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}
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} else if (TextureType == TEXTURE_2D_ARRAY
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|| TextureType == TEXTURE_SHADOW2D_ARRAY) {
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coordType[ELEMENT_Z] = 0;
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}
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for (unsigned i = 0; i < 4; i++) {
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EmitByte(coordType[i], OS);
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}
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// XXX: Emit offsets
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if (hasOffsets)
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for (unsigned i = 2; i < 5; i++)
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EmitByte(MI.getOperand(i).getImm()<<1, OS);
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else
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EmitNullBytes(3, OS);
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// Emit sampler id
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EmitByte(Sampler, OS);
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// XXX:Emit source select
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if ((TextureType == TEXTURE_SHADOW1D
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|| TextureType == TEXTURE_SHADOW2D
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|| TextureType == TEXTURE_SHADOWRECT
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|| TextureType == TEXTURE_SHADOW1D_ARRAY)
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&& Opcode != AMDGPU::TEX_SAMPLE_C_L
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&& Opcode != AMDGPU::TEX_SAMPLE_C_LB) {
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srcSelect[ELEMENT_W] = ELEMENT_Z;
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}
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for (unsigned i = 0; i < 4; i++) {
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EmitByte(srcSelect[i], OS);
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}
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}
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void R600MCCodeEmitter::EmitFCInstr(const MCInst &MI, raw_ostream &OS) const {
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// Emit instruction type
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@ -234,6 +234,80 @@ class VTX_WORD1_GPR {
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let Word1{31} = SRF_MODE_ALL;
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}
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class TEX_WORD0 {
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field bits<32> Word0;
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bits<5> TEX_INST;
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bits<2> INST_MOD;
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bits<1> FETCH_WHOLE_QUAD;
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bits<8> RESOURCE_ID;
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bits<7> SRC_GPR;
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bits<1> SRC_REL;
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bits<1> ALT_CONST;
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bits<2> RESOURCE_INDEX_MODE;
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bits<2> SAMPLER_INDEX_MODE;
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let Word0{4-0} = TEX_INST;
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let Word0{6-5} = INST_MOD;
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let Word0{7} = FETCH_WHOLE_QUAD;
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let Word0{15-8} = RESOURCE_ID;
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let Word0{22-16} = SRC_GPR;
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let Word0{23} = SRC_REL;
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let Word0{24} = ALT_CONST;
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let Word0{26-25} = RESOURCE_INDEX_MODE;
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let Word0{28-27} = SAMPLER_INDEX_MODE;
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}
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class TEX_WORD1 {
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field bits<32> Word1;
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bits<7> DST_GPR;
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bits<1> DST_REL;
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bits<3> DST_SEL_X;
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bits<3> DST_SEL_Y;
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bits<3> DST_SEL_Z;
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bits<3> DST_SEL_W;
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bits<7> LOD_BIAS;
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bits<1> COORD_TYPE_X;
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bits<1> COORD_TYPE_Y;
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bits<1> COORD_TYPE_Z;
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bits<1> COORD_TYPE_W;
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let Word1{6-0} = DST_GPR;
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let Word1{7} = DST_REL;
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let Word1{11-9} = DST_SEL_X;
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let Word1{14-12} = DST_SEL_Y;
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let Word1{17-15} = DST_SEL_Z;
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let Word1{20-18} = DST_SEL_W;
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let Word1{27-21} = LOD_BIAS;
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let Word1{28} = COORD_TYPE_X;
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let Word1{29} = COORD_TYPE_Y;
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let Word1{30} = COORD_TYPE_Z;
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let Word1{31} = COORD_TYPE_W;
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}
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class TEX_WORD2 {
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field bits<32> Word2;
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bits<5> OFFSET_X;
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bits<5> OFFSET_Y;
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bits<5> OFFSET_Z;
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bits<5> SAMPLER_ID;
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bits<3> SRC_SEL_X;
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bits<3> SRC_SEL_Y;
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bits<3> SRC_SEL_Z;
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bits<3> SRC_SEL_W;
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let Word2{4-0} = OFFSET_X;
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let Word2{9-5} = OFFSET_Y;
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let Word2{14-10} = OFFSET_Z;
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let Word2{19-15} = SAMPLER_ID;
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let Word2{22-20} = SRC_SEL_X;
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let Word2{25-23} = SRC_SEL_Y;
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let Word2{28-26} = SRC_SEL_Z;
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let Word2{31-29} = SRC_SEL_W;
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}
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/*
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XXX: R600 subtarget uses a slightly different encoding than the other
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subtargets. We currently handle this in R600MCCodeEmitter, but we may
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@ -386,12 +460,32 @@ class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
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class R600_TEX <bits<11> inst, string opName, list<dag> pattern,
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InstrItinClass itin = AnyALU> :
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InstR600 <inst,
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(outs R600_Reg128:$dst),
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(ins R600_Reg128:$src0, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
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!strconcat(opName, "$dst, $src0, $resourceId, $samplerId, $textureTarget"),
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(outs R600_Reg128:$DST_GPR),
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(ins R600_Reg128:$SRC_GPR, i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID, i32imm:$textureTarget),
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!strconcat(opName, "$DST_GPR, $SRC_GPR, $RESOURCE_ID, $SAMPLER_ID, $textureTarget"),
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pattern,
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itin>{
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let Inst {10-0} = inst;
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itin>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
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let Inst{31-0} = Word0;
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let Inst{63-32} = Word1;
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let TEX_INST = inst{4-0};
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let SRC_REL = 0;
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let DST_REL = 0;
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let DST_SEL_X = 0;
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let DST_SEL_Y = 1;
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let DST_SEL_Z = 2;
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let DST_SEL_W = 3;
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let LOD_BIAS = 0;
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let INST_MOD = 0;
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let FETCH_WHOLE_QUAD = 0;
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let ALT_CONST = 0;
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let SAMPLER_INDEX_MODE = 0;
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let COORD_TYPE_X = 0;
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let COORD_TYPE_Y = 0;
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let COORD_TYPE_Z = 0;
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let COORD_TYPE_W = 0;
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}
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} // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
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@ -867,25 +961,33 @@ def CNDGT_INT : R600_3OP <
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def TEX_LD : R600_TEX <
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0x03, "TEX_LD",
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[(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
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[(set R600_Reg128:$DST_GPR, (int_AMDGPU_txf R600_Reg128:$SRC_GPR,
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imm:$OFFSET_X, imm:$OFFSET_Y, imm:$OFFSET_Z, imm:$RESOURCE_ID,
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imm:$SAMPLER_ID, imm:$textureTarget))]
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> {
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let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $resourceId, $samplerId, $textureTarget";
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let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget);
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let AsmString = "TEX_LD $DST_GPR, $SRC_GPR, $OFFSET_X, $OFFSET_Y, $OFFSET_Z,"
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"$RESOURCE_ID, $SAMPLER_ID, $textureTarget";
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let InOperandList = (ins R600_Reg128:$SRC_GPR, i32imm:$OFFSET_X,
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i32imm:$OFFSET_Y, i32imm:$OFFSET_Z, i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
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i32imm:$textureTarget);
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}
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def TEX_GET_TEXTURE_RESINFO : R600_TEX <
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0x04, "TEX_GET_TEXTURE_RESINFO",
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[(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
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[(set R600_Reg128:$DST_GPR, (int_AMDGPU_txq R600_Reg128:$SRC_GPR,
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imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
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>;
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def TEX_GET_GRADIENTS_H : R600_TEX <
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0x07, "TEX_GET_GRADIENTS_H",
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[(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
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[(set R600_Reg128:$DST_GPR, (int_AMDGPU_ddx R600_Reg128:$SRC_GPR,
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imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
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>;
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def TEX_GET_GRADIENTS_V : R600_TEX <
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0x08, "TEX_GET_GRADIENTS_V",
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[(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
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[(set R600_Reg128:$DST_GPR, (int_AMDGPU_ddy R600_Reg128:$SRC_GPR,
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imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
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>;
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def TEX_SET_GRADIENTS_H : R600_TEX <
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@ -900,32 +1002,38 @@ def TEX_SET_GRADIENTS_V : R600_TEX <
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def TEX_SAMPLE : R600_TEX <
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0x10, "TEX_SAMPLE",
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[(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
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[(set R600_Reg128:$DST_GPR, (int_AMDGPU_tex R600_Reg128:$SRC_GPR,
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imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
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>;
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def TEX_SAMPLE_C : R600_TEX <
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0x18, "TEX_SAMPLE_C",
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[(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
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[(set R600_Reg128:$DST_GPR, (int_AMDGPU_tex R600_Reg128:$SRC_GPR,
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imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
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>;
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def TEX_SAMPLE_L : R600_TEX <
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0x11, "TEX_SAMPLE_L",
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[(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
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[(set R600_Reg128:$DST_GPR, (int_AMDGPU_txl R600_Reg128:$SRC_GPR,
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imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
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>;
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def TEX_SAMPLE_C_L : R600_TEX <
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0x19, "TEX_SAMPLE_C_L",
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[(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
|
||||
[(set R600_Reg128:$DST_GPR, (int_AMDGPU_txl R600_Reg128:$SRC_GPR,
|
||||
imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
|
||||
>;
|
||||
|
||||
def TEX_SAMPLE_LB : R600_TEX <
|
||||
0x12, "TEX_SAMPLE_LB",
|
||||
[(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0,imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
|
||||
[(set R600_Reg128:$DST_GPR, (int_AMDGPU_txb R600_Reg128:$SRC_GPR,
|
||||
imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
|
||||
>;
|
||||
|
||||
def TEX_SAMPLE_C_LB : R600_TEX <
|
||||
0x1A, "TEX_SAMPLE_C_LB",
|
||||
[(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
|
||||
[(set R600_Reg128:$DST_GPR, (int_AMDGPU_txb R600_Reg128:$SRC_GPR,
|
||||
imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
|
||||
>;
|
||||
|
||||
def TEX_SAMPLE_G : R600_TEX <
|
||||
|
||||
Loading…
Reference in New Issue
Block a user