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Fix target-customized spilling in the register scavenger

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This is a follow-up to r178073 (which should actually make target-customized
spilling work again).

I still don't have a regression test for this (but it would be good to have
one; Thumb 1 and Mips16 use this callback as well).

Patch by Richard Sandiford.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178137 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2013-03-27 13:00:56 +00:00
parent d6d0ebbed7
commit 26998ee794
1 changed files with 1 additions and 1 deletions
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2
lib/CodeGen/RegisterScavenging.cpp
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@ -371,7 +371,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
if (Scavenged[SI].Reg == 0)
break;
if (SI < Scavenged.size()) {
if (SI == Scavenged.size()) {
// We need to scavenge a register but have no spill slot, the target
// must know how to do it (if not, we'll assert below).
Scavenged.push_back(ScavengedInfo());