From 269bc0042fc976b13b44c97c6546b4d726073940 Mon Sep 17 00:00:00 2001
From: Richard Osborne <richard@xmos.com>
Date: Wed, 3 Dec 2008 10:59:16 +0000
Subject: [PATCH] Add support for ISD::TRAP to the XCore backend

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60479 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/XCore/XCoreISelLowering.cpp |  2 ++
 lib/Target/XCore/XCoreInstrInfo.td     | 15 ++++++++++++++-
 test/CodeGen/XCore/trap.ll             | 11 +++++++++++
 3 files changed, 27 insertions(+), 1 deletion(-)
 create mode 100644 test/CodeGen/XCore/trap.ll

diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp
index e24b998ae25..e2d2ab7c898 100644
--- a/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/lib/Target/XCore/XCoreISelLowering.cpp
@@ -106,6 +106,8 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
   setOperationAction(ISD::ROTL , MVT::i32, Expand);
   setOperationAction(ISD::ROTR , MVT::i32, Expand);
   
+  setOperationAction(ISD::TRAP, MVT::Other, Legal);
+  
   // Expand jump tables for now
   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
   setOperationAction(ISD::JumpTable, MVT::i32, Custom);
diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td
index 031ad875fa8..4ee1f63e638 100644
--- a/lib/Target/XCore/XCoreInstrInfo.td
+++ b/lib/Target/XCore/XCoreInstrInfo.td
@@ -762,7 +762,7 @@ def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
 
 // One operand short
 // TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp
-// bru, setdp, setcp, setv, setev, kcall, ecallt, ecallf
+// bru, setdp, setcp, setv, setev, kcall
 // dgetreg
 let isBranch=1, isIndirectBranch=1, isTerminator=1 in
 def BAU_1r : _F1R<(outs), (ins GRRegs:$addr),
@@ -774,6 +774,16 @@ def SETSP_1r : _F1R<(outs), (ins GRRegs:$src),
                  "set sp, $src",
                  []>;
 
+let isBarrier = 1, hasCtrlDep = 1 in 
+def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src),
+                 "ecallt $src",
+                 []>;
+
+let isBarrier = 1, hasCtrlDep = 1 in 
+def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src),
+                 "ecallf $src",
+                 []>;
+
 let isCall=1, 
 // All calls clobber the the link register and the non-callee-saved registers:
 Defs = [R0, R1, R2, R3, R11, LR] in {
@@ -852,6 +862,9 @@ def : Pat<(store GRRegs:$val, GRRegs:$addr),
 /// cttz
 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
 
+/// trap
+def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
+
 ///
 /// branch patterns
 ///
diff --git a/test/CodeGen/XCore/trap.ll b/test/CodeGen/XCore/trap.ll
new file mode 100644
index 00000000000..b3d3bc2270e
--- /dev/null
+++ b/test/CodeGen/XCore/trap.ll
@@ -0,0 +1,11 @@
+; RUN: llvm-as < %s | llc -march=xcore > %t1.s
+; RUN: grep "ecallf" %t1.s | count 1
+; RUN: grep "ldc" %t1.s | count 1
+define i32 @test() noreturn nounwind  {
+entry:
+	tail call void @llvm.trap( )
+	unreachable
+}
+
+declare void @llvm.trap() nounwind 
+