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[mips] DSP-ASE move from HI/LO register instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179739 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -143,6 +143,16 @@ static DecodeStatus DecodeACRegsDSPRegisterClass(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeHIRegsDSPRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLORegsDSPRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBranchTarget(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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@ -496,6 +506,30 @@ static DecodeStatus DecodeACRegsDSPRegisterClass(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeHIRegsDSPRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo >= 4)
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return MCDisassembler::Fail;
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unsigned Reg = getReg(Decoder, Mips::HIRegsDSPRegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeLORegsDSPRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo >= 4)
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return MCDisassembler::Fail;
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unsigned Reg = getReg(Decoder, Mips::LORegsDSPRegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeBranchTarget(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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@ -219,6 +219,33 @@ class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
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let Inst{5-0} = funct;
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}
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// MFHI sub-class format.
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class MFHI_FMT<bits<6> funct> : DSPInst {
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bits<5> rd;
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bits<2> ac;
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let Inst{31-26} = 0;
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let Inst{25-23} = 0;
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let Inst{22-21} = ac;
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let Inst{20-16} = 0;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0;
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let Inst{5-0} = funct;
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}
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// MTHI sub-class format.
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class MTHI_FMT<bits<6> funct> : DSPInst {
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bits<5> rs;
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bits<2> ac;
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let Inst{31-26} = 0;
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let Inst{25-21} = rs;
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let Inst{20-13} = 0;
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let Inst{12-11} = ac;
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let Inst{10-6} = 0;
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let Inst{5-0} = funct;
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}
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// EXTR.W sub-class format (type 1).
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class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
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bits<5> rt;
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@ -145,6 +145,10 @@ class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
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class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
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class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
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class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
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class MFHI_ENC : MFHI_FMT<0b010000>;
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class MFLO_ENC : MFHI_FMT<0b010010>;
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class MTHI_ENC : MTHI_FMT<0b010001>;
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class MTLO_ENC : MTHI_FMT<0b010011>;
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class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
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class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
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class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
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@ -482,6 +486,20 @@ class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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string Constraints = "$acin = $ac";
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}
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class MFHI_DESC_BASE<string instr_asm, RegisterClass RC, InstrItinClass itin> {
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dag OutOperandList = (outs CPURegs:$rd);
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dag InOperandList = (ins RC:$ac);
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string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
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InstrItinClass Itinerary = itin;
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}
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class MTHI_DESC_BASE<string instr_asm, RegisterClass RC, InstrItinClass itin> {
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dag OutOperandList = (outs RC:$ac);
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dag InOperandList = (ins CPURegs:$rs);
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string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
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InstrItinClass Itinerary = itin;
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}
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class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
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MipsPseudo<(outs CPURegs:$dst), (ins), [(set CPURegs:$dst, (OpNode))]> {
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list<Register> Uses = [DSPCtrl];
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@ -725,6 +743,12 @@ class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>;
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class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>;
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// Move from/to hi/lo.
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class MFHI_DESC : MFHI_DESC_BASE<"mfhi", HIRegsDSP, NoItinerary>;
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class MFLO_DESC : MFHI_DESC_BASE<"mflo", LORegsDSP, NoItinerary>;
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class MTHI_DESC : MTHI_DESC_BASE<"mthi", HIRegsDSP, NoItinerary>;
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class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LORegsDSP, NoItinerary>;
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// Dot product with accumulate/subtract
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class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
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@ -1094,6 +1118,10 @@ def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
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def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
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def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
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def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
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def MFHI_DSP : MFHI_ENC, MFHI_DESC;
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def MFLO_DSP : MFLO_ENC, MFLO_DESC;
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def MTHI_DSP : MTHI_ENC, MTHI_DESC;
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def MTLO_DSP : MTLO_ENC, MTLO_DESC;
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def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
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def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
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def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
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@ -229,14 +229,14 @@ let Namespace = "Mips" in {
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def D31_64 : AFPR64<31, "f31", [F31]>, DwarfRegNum<[63]>;
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// Hi/Lo registers
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def HI : Register<"hi">, DwarfRegNum<[64]>;
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def HI1 : Register<"hi1">, DwarfRegNum<[176]>;
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def HI2 : Register<"hi2">, DwarfRegNum<[178]>;
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def HI3 : Register<"hi3">, DwarfRegNum<[180]>;
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def LO : Register<"lo">, DwarfRegNum<[65]>;
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def LO1 : Register<"lo1">, DwarfRegNum<[177]>;
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def LO2 : Register<"lo2">, DwarfRegNum<[179]>;
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def LO3 : Register<"lo3">, DwarfRegNum<[181]>;
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def HI : Register<"ac0">, DwarfRegNum<[64]>;
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def HI1 : Register<"ac1">, DwarfRegNum<[176]>;
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def HI2 : Register<"ac2">, DwarfRegNum<[178]>;
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def HI3 : Register<"ac3">, DwarfRegNum<[180]>;
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def LO : Register<"ac0">, DwarfRegNum<[65]>;
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def LO1 : Register<"ac1">, DwarfRegNum<[177]>;
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def LO2 : Register<"ac2">, DwarfRegNum<[179]>;
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def LO3 : Register<"ac3">, DwarfRegNum<[181]>;
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let SubRegIndices = [sub_32] in {
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def HI64 : RegisterWithSubRegs<"hi", [HI]>;
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@ -342,6 +342,8 @@ def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>, Unallocatable;
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// Hi/Lo Registers
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def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>, Unallocatable;
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def HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)>, Unallocatable;
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def LORegsDSP : RegisterClass<"Mips", [i32], 32, (add LO, LO1, LO2, LO3)>;
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def HIRegsDSP : RegisterClass<"Mips", [i32], 32, (add HI, HI1, HI2, HI3)>;
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// Hardware registers
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def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable;
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13
test/MC/Disassembler/Mips/mips-dsp.txt
Normal file
13
test/MC/Disassembler/Mips/mips-dsp.txt
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@ -0,0 +1,13 @@
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# RUN: llvm-mc -triple=mipsel-unknown-linux -mattr=+dsp -disassemble < %s | FileCheck %s
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# CHECK: mfhi $21, $ac3
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0x10 0xa8 0x60 0x00
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# CHECK: mflo $21, $ac3
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0x12 0xa8 0x60 0x00
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# CHECK: mthi $21, $ac3
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0x11 0x18 0xa0 0x02
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# CHECK: mtlo $21, $ac3
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0x13 0x18 0xa0 0x02
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