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Add some missing checks in TwoAddressInstructionPass::CoalesceExtSubRegs.

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Check that all the instructions are in the same basic block, that the
EXTRACT_SUBREGs write to the same subregs that are being extracted, and that
the source and destination registers are in the same regclass.  Some of
these constraints can be relaxed with a bit more work.  Jakob suggested
that the loop that checks for subregs when NewSubIdx != 0 should use the
"nodbg" iterator, so I made that change here, too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105437 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-06-03 23:53:58 +00:00
parent 6ee358b4eb
commit 26bf8f9a1b
1 changed files with 21 additions and 4 deletions
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25
lib/CodeGen/TwoAddressInstructionPass.cpp
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@ -1164,6 +1164,12 @@ TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs,
if (!Seen.insert(SrcReg))
continue;
// Check that the instructions are all in the same basic block.
MachineInstr *SrcDefMI = MRI->getVRegDef(SrcReg);
MachineInstr *DstDefMI = MRI->getVRegDef(DstReg);
if (SrcDefMI->getParent() != DstDefMI->getParent())
continue;
// If there are no other uses than extract_subreg which feed into
// the reg_sequence, then we might be able to coalesce them.
bool CanCoalesce = true;
@ -1172,25 +1178,36 @@ TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs,
UI = MRI->use_nodbg_begin(SrcReg),
UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
MachineInstr *UseMI = &*UI;
unsigned SubRegIdx = UseMI->getOperand(2).getImm();
// FIXME: For now require that the destination subregs match the subregs
// being extracted.
if (!UseMI->isExtractSubreg() ||
UseMI->getOperand(0).getReg() != DstReg) {
UseMI->getOperand(0).getReg() != DstReg ||
UseMI->getOperand(0).getSubReg() != SubRegIdx ||
UseMI->getOperand(1).getSubReg() != 0) {
CanCoalesce = false;
break;
}
SubIndices.push_back(UseMI->getOperand(2).getImm());
SubIndices.push_back(SubRegIdx);
}
if (!CanCoalesce || SubIndices.size() < 2)
continue;
// FIXME: For now require that the src and dst registers are in the
// same regclass.
if (MRI->getRegClass(SrcReg) != MRI->getRegClass(DstReg))
continue;
std::sort(SubIndices.begin(), SubIndices.end());
unsigned NewSubIdx = 0;
if (TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SubIndices,
NewSubIdx)) {
bool Proceed = true;
if (NewSubIdx)
for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
RE = MRI->reg_end(); RI != RE; ) {
for (MachineRegisterInfo::reg_nodbg_iterator
RI = MRI->reg_nodbg_begin(SrcReg), RE = MRI->reg_nodbg_end();
RI != RE; ) {
MachineOperand &MO = RI.getOperand();
++RI;
// FIXME: If the sub-registers do not combine to the whole