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Fix encoding of 'sf' and 'sfh' instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103399 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -655,7 +655,7 @@ def SFHvec:
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def SFHr16:
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def SFHr16:
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RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
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RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
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"sfh\t$rT, $rA, $rB", IntegerOp,
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"sfh\t$rT, $rA, $rB", IntegerOp,
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[(set R16C:$rT, (sub R16C:$rA, R16C:$rB))]>;
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[(set R16C:$rT, (sub R16C:$rB, R16C:$rA))]>;
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def SFHIvec:
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def SFHIvec:
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RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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@ -670,11 +670,11 @@ def SFHIr16 : RI10Form<0b10110000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
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def SFvec : RRForm<0b00000010000, (outs VECREG:$rT),
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def SFvec : RRForm<0b00000010000, (outs VECREG:$rT),
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(ins VECREG:$rA, VECREG:$rB),
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(ins VECREG:$rA, VECREG:$rB),
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"sf\t$rT, $rA, $rB", IntegerOp,
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"sf\t$rT, $rA, $rB", IntegerOp,
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[(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
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[(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rB), (v4i32 VECREG:$rA)))]>;
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def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
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def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
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"sf\t$rT, $rA, $rB", IntegerOp,
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"sf\t$rT, $rA, $rB", IntegerOp,
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[(set R32C:$rT, (sub R32C:$rA, R32C:$rB))]>;
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[(set R32C:$rT, (sub R32C:$rB, R32C:$rA))]>;
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def SFIvec:
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def SFIvec:
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RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
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26
test/CodeGen/CellSPU/sub_ops.ll
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26
test/CodeGen/CellSPU/sub_ops.ll
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@ -0,0 +1,26 @@
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; RUN: llc < %s -march=cellspu | FileCheck %s
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define i32 @subword( i32 %param1, i32 %param2) {
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; Check ordering of registers ret=param1-param2 -> rt=rb-ra
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; CHECK-NOT: sf $3, $3, $4
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; CHECK: sf $3, $4, $3
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%1 = sub i32 %param1, %param2
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ret i32 %1
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}
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define i16 @subhword( i16 %param1, i16 %param2) {
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; Check ordering of registers ret=param1-param2 -> rt=rb-ra
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; CHECK-NOT: sfh $3, $3, $4
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; CHECK: sfh $3, $4, $3
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%1 = sub i16 %param1, %param2
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ret i16 %1
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}
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define float @subfloat( float %param1, float %param2) {
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; Check ordering of registers ret=param1-param2 -> rt=ra-rb
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; (yes this is reverse of i32 instruction)
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; CHECK-NOT: fs $3, $4, $3
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; CHECK: fs $3, $3, $4
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%1 = fsub float %param1, %param2
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ret float %1
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}
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