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CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78559 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -21,8 +21,8 @@
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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STATISTIC(NumNarrows, "Number of 32-bit instructions reduced to 16-bit ones");
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STATISTIC(Num2Addrs, "Number of 32-bit instructions reduced to 2-address");
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STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones");
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STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones");
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namespace {
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/// ReduceTable - A static table with information on mapping from wide
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@ -63,8 +63,9 @@ namespace {
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{ ARM::t2LSRrr, ARM::tLSRrr, 0, 0, 0, 1, 0, 0,0, 0 },
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{ ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0 },
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// FIXME: Do we need the 16-bit 'S' variant?
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// FIXME: t2MOVcc
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{ ARM::t2MOVr,ARM::tMOVgpr2gpr,0, 0, 0, 0, 0, 1,0, 0 },
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{ ARM::t2MUL, ARM::tMUL, 0, 0, 0, 1, 0, 0,0, 0 },
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{ ARM::t2MUL, 0, ARM::tMUL, 0, 0, 1, 0, 0,0, 0 },
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{ ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0 },
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{ ARM::t2ORRrr, ARM::tORR, 0, 0, 0, 1, 0, 0,0, 0 },
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{ ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 0,0, 0 },
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@ -126,10 +127,8 @@ Thumb2SizeReduce::Thumb2SizeReduce() : MachineFunctionPass(&ID) {
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}
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static bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
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bool is2Addr, bool LiveCPSR,
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bool &HasCC, bool &CCDead) {
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unsigned PredReg = 0;
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ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
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bool is2Addr, ARMCC::CondCodes Pred,
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bool LiveCPSR, bool &HasCC, bool &CCDead) {
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if ((is2Addr && Entry.PredCC2 == 0) ||
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(!is2Addr && Entry.PredCC1 == 0)) {
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if (Pred == ARMCC::AL) {
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@ -181,6 +180,19 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
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return false;
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}
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// Check if it's possible / necessary to transfer the predicate.
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const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc2);
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unsigned PredReg = 0;
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ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
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bool SkipPred = false;
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if (Pred != ARMCC::AL) {
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if (!NewTID.isPredicable())
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// Can't transfer predicate, fail.
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return false;
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} else {
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SkipPred = !NewTID.isPredicable();
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}
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bool HasCC = false;
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bool CCDead = false;
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if (TID.hasOptionalDef()) {
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@ -189,7 +201,7 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
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if (HasCC && MI->getOperand(NumOps-1).isDead())
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CCDead = true;
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}
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if (!VerifyPredAndCC(MI, Entry, true, LiveCPSR, HasCC, CCDead))
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if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
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return false;
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// Add the 16-bit instruction.
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@ -201,15 +213,18 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
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// Transfer the rest of operands.
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unsigned NumOps = TID.getNumOperands();
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for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i)
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if (!(i < NumOps && TID.OpInfo[i].isOptionalDef()))
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MIB.addOperand(MI->getOperand(i));
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for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
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if (i < NumOps && TID.OpInfo[i].isOptionalDef())
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continue;
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if (SkipPred && TID.OpInfo[i].isPredicate())
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continue;
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MIB.addOperand(MI->getOperand(i));
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}
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DOUT << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB;
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MBB.erase(MI);
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++Num2Addrs;
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++NumNarrows;
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return true;
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}
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@ -238,6 +253,19 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
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}
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}
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// Check if it's possible / necessary to transfer the predicate.
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const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc1);
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unsigned PredReg = 0;
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ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
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bool SkipPred = false;
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if (Pred != ARMCC::AL) {
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if (!NewTID.isPredicable())
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// Can't transfer predicate, fail.
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return false;
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} else {
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SkipPred = !NewTID.isPredicable();
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}
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bool HasCC = false;
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bool CCDead = false;
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if (TID.hasOptionalDef()) {
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@ -246,7 +274,7 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
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if (HasCC && MI->getOperand(NumOps-1).isDead())
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CCDead = true;
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}
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if (!VerifyPredAndCC(MI, Entry, false, LiveCPSR, HasCC, CCDead))
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if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
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return false;
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// Add the 16-bit instruction.
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@ -258,15 +286,18 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
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// Transfer the rest of operands.
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unsigned NumOps = TID.getNumOperands();
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for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i)
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if (!(i < NumOps && TID.OpInfo[i].isOptionalDef()))
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MIB.addOperand(MI->getOperand(i));
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for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
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if (i < NumOps && TID.OpInfo[i].isOptionalDef())
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continue;
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if (SkipPred && TID.OpInfo[i].isPredicate())
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continue;
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MIB.addOperand(MI->getOperand(i));
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}
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DOUT << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB;
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MBB.erase(MI);
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++Num2Addrs;
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++NumNarrows;
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return true;
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}
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@ -298,9 +329,16 @@ static bool UpdateCPSRLiveness(MachineInstr &MI, bool LiveCPSR) {
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bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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// FIXME: Track whether CPSR is live. If not, then it's possible to convert
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// one that doesn't set CPSR to one that does.
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bool LiveCPSR = false;
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// Yes, CPSR could be livein.
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for (MachineBasicBlock::const_livein_iterator I = MBB.livein_begin(),
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E = MBB.livein_end(); I != E; ++I) {
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if (*I == ARM::CPSR) {
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LiveCPSR = true;
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break;
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}
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}
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MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
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MachineBasicBlock::iterator NextMII = next(MII);
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for (; MII != E; MII = NextMII) {
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