6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-23 17:24:48 +00:00
Code Issues Projects Releases Wiki Activity

Continue to tighten decoding by performing more operand validation.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2011-08-11 20:21:46 +00:00
parent ade7d00f5a
commit 26d2f0ac91
6 changed files with 80 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -133,6 +133,8 @@ static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
@ -759,6 +761,8 @@ static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
// Empty register lists are not allowed.
if (CountPopulation_32(Val) == 0) return false;
for (unsigned i = 0; i < 16; ++i) {
if (Val & (1 << i)) {
if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false;
@ -2467,3 +2471,9 @@ static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
return true;
}
static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (!Val) return false;
Inst.addOperand(MCOperand::CreateImm(Val));
return true;
}