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Fix a minor bug (ORo didn't mark that it set CR0).

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Refactor how . instructions are handled.  In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.

For example, instead of this:

-def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31,  28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-                   "and. $rA, $rS, $rB">;

We now have this:

+def AND  : XForm_6<31,  28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "and $rA, $rS, $rB">;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21225 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-04-11 15:01:39 +00:00
parent 21478e55db
commit 26d4fdb968
2 changed files with 37 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
lib/Target/PowerPC/PPCInstrFormats.td
View File

@@ -10,6 +10,14 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// DOT - This is a marker that should be added to instructions that set the
// flags in CR0.
class DOT {
list<Register> Defs = [CR0];
bit RC = 1;
}
class Format<bits<5> val> { class Format<bits<5> val> {
bits<5> Value = val; bits<5> Value = val;
} }
@@ -217,18 +225,19 @@ class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
// This is the same as XForm_base_r3xo, but the first two operands are swapped // This is the same as XForm_base_r3xo, but the first two operands are swapped
// when code is emitted. // when code is emitted.
class XForm_base_r3xo_swapped class XForm_base_r3xo_swapped
<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx, <bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
dag OL, string asmstr> dag OL, string asmstr>
: I<opcode, ppc64, vmx, OL, asmstr> { : I<opcode, ppc64, vmx, OL, asmstr> {
bits<5> A; bits<5> A;
bits<5> RST; bits<5> RST;
bits<5> B; bits<5> B;
bit RC = 0;
let Inst{6-10} = RST; let Inst{6-10} = RST;
let Inst{11-15} = A; let Inst{11-15} = A;
let Inst{16-20} = B; let Inst{16-20} = B;
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = rc; let Inst{31} = RC;
} }
@@ -243,9 +252,10 @@ class XForm_5<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
let B = 0; let B = 0;
} }
class XForm_6<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx, class XForm_6<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
dag OL, string asmstr> dag OL, string asmstr>
: XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr>; : XForm_base_r3xo_swapped<opcode, xo, ppc64, vmx, OL, asmstr> {
}
class XForm_8<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx, class XForm_8<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
dag OL, string asmstr> dag OL, string asmstr>
@@ -253,13 +263,15 @@ class XForm_8<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
class XForm_10<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx, class XForm_10<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
dag OL, string asmstr> dag OL, string asmstr>
: XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr> { : XForm_base_r3xo_swapped<opcode, xo, ppc64, vmx, OL, asmstr> {
let RC = rc;
} }
class XForm_11<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx, class XForm_11<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
dag OL, string asmstr> dag OL, string asmstr>
: XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr> { : XForm_base_r3xo_swapped<opcode, xo, ppc64, vmx, OL, asmstr> {
let B = 0; let B = 0;
let RC = rc;
} }
class XForm_16<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx, class XForm_16<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,

39
lib/Target/PowerPC/PPCInstrInfo.td
View File

@@ -1,4 +1,3 @@
//===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=// //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
@@ -222,38 +221,38 @@ def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
"ldx $dst, $base, $index">; "ldx $dst, $base, $index">;
} }
def MFCR : XForm_5<31, 19, 0, 0, (ops GPRC:$dst), "mfcr $dst">; def MFCR : XForm_5<31, 19, 0, 0, (ops GPRC:$dst), "mfcr $dst">;
def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def AND : XForm_6<31, 28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"and $rA, $rS, $rB">; "and $rA, $rS, $rB">;
let Defs = [CR0] in
def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def ANDo : XForm_6<31, 28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"and. $rA, $rS, $rB">; "and. $rA, $rS, $rB">, DOT;
def ANDC : XForm_6<31, 60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def ANDC : XForm_6<31, 60, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"andc $rA, $rS, $rB">; "andc $rA, $rS, $rB">;
def EQV : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def EQV : XForm_6<31, 284, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"eqv $rA, $rS, $rB">; "eqv $rA, $rS, $rB">;
def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def NAND : XForm_6<31, 476, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"nand $rA, $rS, $rB">; "nand $rA, $rS, $rB">;
def NOR : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def NOR : XForm_6<31, 124, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"nor $rA, $rS, $rB">; "nor $rA, $rS, $rB">;
def OR : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def OR : XForm_6<31, 444, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"or $rA, $rS, $rB">; "or $rA, $rS, $rB">;
def ORo : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def ORo : XForm_6<31, 444, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"or. $rA, $rS, $rB">; "or. $rA, $rS, $rB">, DOT;
def ORC : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def ORC : XForm_6<31, 412, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"orc $rA, $rS, $rB">; "orc $rA, $rS, $rB">;
def SLD : XForm_6<31, 27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def SLD : XForm_6<31, 27, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"sld $rA, $rS, $rB">; "sld $rA, $rS, $rB">;
def SLW : XForm_6<31, 24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def SLW : XForm_6<31, 24, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"slw $rA, $rS, $rB">; "slw $rA, $rS, $rB">;
def SRD : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def SRD : XForm_6<31, 539, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"srd $rA, $rS, $rB">; "srd $rA, $rS, $rB">;
def SRW : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def SRW : XForm_6<31, 536, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"srw $rA, $rS, $rB">; "srw $rA, $rS, $rB">;
def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def SRAD : XForm_6<31, 794, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"srad $rA, $rS, $rB">; "srad $rA, $rS, $rB">;
def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def SRAW : XForm_6<31, 792, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"sraw $rA, $rS, $rB">; "sraw $rA, $rS, $rB">;
def XOR : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), def XOR : XForm_6<31, 316, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"xor $rA, $rS, $rB">; "xor $rA, $rS, $rB">;
let isStore = 1 in { let isStore = 1 in {
def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),