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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-18 12:29:21 +00:00
all but CAS working on x86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47798 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1165,23 +1165,24 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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assert(((Node->getNumOperands() == 4 && Node->getOpcode() == ISD::ATOMIC_LCS) ||
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(Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_LAS) ||
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(Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_SWAP)) &&
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"Invalid MemBarrier node!");
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"Invalid Atomic node!");
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int num = Node->getOpcode() == ISD::ATOMIC_LCS ? 4 : 3;
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MVT::ValueType VT = Node->getValueType(0);
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switch (TLI.getOperationAction(ISD::ATOMIC_LCS, VT)) {
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SDOperand Ops[4];
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for (int x = 0; x < num; ++x)
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Ops[x] = LegalizeOp(Node->getOperand(x));
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Result = DAG.UpdateNodeOperands(Result, &Ops[0], num);
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switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal: {
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SDOperand Ops[4];
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for (int x = 0; x < num; ++x)
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Ops[x] = LegalizeOp(Node->getOperand(x));
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Result = DAG.UpdateNodeOperands(Result, &Ops[0], num);
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AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
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AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
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return Result.getValue(Op.ResNo);
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case TargetLowering::Custom:
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Result = TLI.LowerOperation(Result, DAG);
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break;
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case TargetLowering::Legal:
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break;
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}
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}
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break;
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AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
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AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
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return Result.getValue(Op.ResNo);
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}
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case ISD::Constant: {
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@ -283,6 +283,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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if (!Subtarget->hasSSE2())
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setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
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setOperationAction(ISD::ATOMIC_LCS , MVT::i8, Custom);
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setOperationAction(ISD::ATOMIC_LCS , MVT::i16, Custom);
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setOperationAction(ISD::ATOMIC_LCS , MVT::i32, Custom);
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// Use the default ISD::LOCATION, ISD::DECLARE expansion.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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@ -5345,11 +5348,35 @@ SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) {
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return Op;
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}
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SDOperand X86TargetLowering::LowerCAS(SDOperand Op, SelectionDAG &DAG) {
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MVT::ValueType T = cast<AtomicSDNode>(Op.Val)->getVT();
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unsigned Reg;
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unsigned size;
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switch(T) {
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case MVT::i8: Reg = X86::AL; size = 1; break;
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case MVT::i16: Reg = X86::AX; size = 2; break;
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case MVT::i32: Reg = X86::EAX; size = 4; break;
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};
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SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
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Op.getOperand(2), SDOperand());
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SDOperand Ops[] = { cpIn.getValue(0),
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Op.getOperand(1),
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Op.getOperand(3),
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DAG.getTargetConstant(size, MVT::i8),
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cpIn.getValue(1) };
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SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
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SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
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SDOperand cpOut =
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DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
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return cpOut;
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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default: assert(0 && "Should not custom lower this!");
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case ISD::ATOMIC_LCS: return LowerCAS(Op,DAG);
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case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
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case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
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case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
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@ -5454,6 +5481,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
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case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
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case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
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case X86ISD::LCMPXCHG_DAG: return "x86ISD::LCMPXCHG_DAG";
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}
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}
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@ -208,6 +208,9 @@ namespace llvm {
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// operand #3 optional in flag
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TC_RETURN,
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// compare and swap
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LCMPXCHG_DAG,
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// Store FP control world into i16 memory
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FNSTCW16m
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};
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@ -540,6 +543,7 @@ namespace llvm {
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SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerCAS(SDOperand Op, SelectionDAG &DAG);
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SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
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SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
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};
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@ -35,6 +35,9 @@ def SDTX86SetCC : SDTypeProfile<1, 2,
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[SDTCisVT<0, i8>,
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SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
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def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
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SDTCisVT<2, i8>]>;
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def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
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def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
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@ -69,6 +72,10 @@ def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
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[SDNPHasChain]>;
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def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
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def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
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[SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
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SDNPMayLoad]>;
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def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
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[SDNPHasChain, SDNPOptInFlag]>;
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@ -2539,28 +2546,29 @@ def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
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// Atomic support
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//
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//FIXME: Please check the format
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let Defs = [EAX], Uses = [EAX] in {
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def CMPXCHG32 : I<0xB1, Pseudo, (outs), (ins GR32:$ptr, GR32:$swap),
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"cmpxchgl $swap,($ptr)", []>, TB;
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def LCMPXCHG32 : I<0xB1, Pseudo, (outs), (ins GR32:$ptr, GR32:$swap),
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"lock cmpxchgl $swap,($ptr)", []>, TB, LOCK;
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//FIXME: Please check the format Pseudo is certainly wrong, but the opcode and
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// prefixes should be correct
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let Defs = [EAX, EFLAGS], Uses = [EAX] in {
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def CMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap),
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"cmpxchgl $swap,$ptr", []>, TB;
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def LCMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap),
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"lock cmpxchgl $swap,$ptr", [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
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}
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let Defs = [AX], Uses = [AX] in {
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def CMPXCHG16 : I<0xB1, Pseudo, (outs), (ins GR32:$ptr, GR16:$swap),
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let Defs = [AX, EFLAGS], Uses = [AX] in {
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def CMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, GR16:$swap),
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"cmpxchgw $swap,($ptr)", []>, TB, OpSize;
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def LCMPXCHG16 : I<0xB1, Pseudo, (outs), (ins GR32:$ptr, GR16:$swap),
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"cmpxchgw $swap,($ptr)", []>, TB, OpSize, LOCK;
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def LCMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, GR16:$swap),
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"lock cmpxchgw $swap,$ptr", [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
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}
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let Defs = [AL], Uses = [AL] in {
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def CMPXCHG8 : I<0xB0, Pseudo, (outs), (ins GR32:$ptr, GR8:$swap),
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let Defs = [AL, EFLAGS], Uses = [AL] in {
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def CMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap),
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"cmpxchgb $swap,($ptr)", []>, TB;
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def LCMPXCHG8 : I<0xB0, Pseudo, (outs), (ins GR32:$ptr, GR8:$swap),
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"cmpxchgb $swap,($ptr)", []>, TB, LOCK;
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def LCMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap),
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"lock cmpxchgb $swap,$ptr", [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
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}
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let Constraints = "$val = $dst" in {
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let Constraints = "$val = $dst", Defs = [EFLAGS] in {
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def LXADD32 : I<0xC1, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
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"lock xadd $val, $ptr",
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[(set GR32:$dst, (atomic_las_32 addr:$ptr, GR32:$val))]>,
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@ -2598,23 +2606,6 @@ def XCHG8 : I<0x86, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
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"lock xchg $val, $ptr", []>;
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}
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//FIXME: these are a hack until the patterns using the LCMPXCHG written
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let Defs = [EAX], Uses = [EAX] in
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def PLCMPXCHG32 : I<0, Pseudo, (outs GR32:$dst),
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(ins i32mem:$ptr, GR32:$cmp, GR32:$swap),
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"movl $cmp, %eax \n lock \n cmpxchgl $swap,$ptr \n movl %eax, $dst",
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[(set GR32:$dst, (atomic_lcs_32 addr:$ptr, GR32:$cmp, GR32:$swap))]>;
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let Defs = [AX] in
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def PLCMPXCHG16 : I<0, Pseudo, (outs GR16:$dst),
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(ins i16mem:$ptr, GR16:$cmp, GR16:$swap),
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"movw $cmp, %ax \n lock \n cmpxchgw $swap,$ptr \n movw %ax, $dst",
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[(set GR16:$dst, (atomic_lcs_16 addr:$ptr, GR16:$cmp, GR16:$swap))]>;
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let Defs = [AL] in
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def PLCMPXCHG8 : I<0, Pseudo, (outs GR8:$dst),
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(ins i8mem:$ptr, GR8:$cmp, GR8:$swap),
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"movb $cmp, %al \n lock cmpxchgb $swap,$ptr \n movb %al, $dst",
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[(set GR8:$dst, (atomic_lcs_8 addr:$ptr, GR8:$cmp, GR8:$swap))]>;
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//===----------------------------------------------------------------------===//
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