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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-03 18:29:48 +00:00
Removed un-used code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108841 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1968,54 +1968,6 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
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false, false, 0);
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}
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SDValue
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ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
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SelectionDAG &DAG) const {
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SDNode *Node = Op.getNode();
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DebugLoc dl = Node->getDebugLoc();
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EVT VT = Node->getValueType(0);
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SDValue Chain = Op.getOperand(0);
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SDValue Size = Op.getOperand(1);
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SDValue Align = Op.getOperand(2);
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// Chain the dynamic stack allocation so that it doesn't modify the stack
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// pointer when other instructions are using the stack.
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
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unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
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unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
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if (AlignVal > StackAlign)
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// Do this now since selection pass cannot introduce new target
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// independent node.
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Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
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// In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
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// using a "add r, sp, r" instead. Negate the size now so we don't have to
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// do even more horrible hack later.
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MachineFunction &MF = DAG.getMachineFunction();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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if (AFI->isThumb1OnlyFunction()) {
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bool Negate = true;
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
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if (C) {
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uint32_t Val = C->getZExtValue();
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if (Val <= 508 && ((Val & 3) == 0))
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Negate = false;
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}
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if (Negate)
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Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
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}
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SDVTList VTList = DAG.getVTList(VT, MVT::Other);
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SDValue Ops1[] = { Chain, Size, Align };
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SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
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Chain = Res.getValue(1);
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Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
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DAG.getIntPtrConstant(0, true), SDValue());
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SDValue Ops2[] = { Res, Chain };
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return DAG.getMergeValues(Ops2, 2, dl);
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}
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SDValue
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ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
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SDValue &Root, SelectionDAG &DAG,
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@ -3622,7 +3574,6 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::BR_CC: return LowerBR_CC(Op, DAG);
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case ISD::BR_JT: return LowerBR_JT(Op, DAG);
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case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
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case ISD::VASTART: return LowerVASTART(Op, DAG);
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case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
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case ISD::SINT_TO_FP:
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