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Removed un-used code.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108841 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-07-20 14:51:32 +00:00
parent 6089e464dd
commit 26ede6834e
1 changed files with 0 additions and 49 deletions
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49
lib/Target/ARM/ARMISelLowering.cpp
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@ -1968,54 +1968,6 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
false, false, 0);
}
SDValue
ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
SelectionDAG &DAG) const {
SDNode *Node = Op.getNode();
DebugLoc dl = Node->getDebugLoc();
EVT VT = Node->getValueType(0);
SDValue Chain = Op.getOperand(0);
SDValue Size = Op.getOperand(1);
SDValue Align = Op.getOperand(2);
// Chain the dynamic stack allocation so that it doesn't modify the stack
// pointer when other instructions are using the stack.
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
if (AlignVal > StackAlign)
// Do this now since selection pass cannot introduce new target
// independent node.
Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
// In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
// using a "add r, sp, r" instead. Negate the size now so we don't have to
// do even more horrible hack later.
MachineFunction &MF = DAG.getMachineFunction();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
if (AFI->isThumb1OnlyFunction()) {
bool Negate = true;
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
if (C) {
uint32_t Val = C->getZExtValue();
if (Val <= 508 && ((Val & 3) == 0))
Negate = false;
}
if (Negate)
Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
}
SDVTList VTList = DAG.getVTList(VT, MVT::Other);
SDValue Ops1[] = { Chain, Size, Align };
SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
Chain = Res.getValue(1);
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
DAG.getIntPtrConstant(0, true), SDValue());
SDValue Ops2[] = { Res, Chain };
return DAG.getMergeValues(Ops2, 2, dl);
}
SDValue
ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
SDValue &Root, SelectionDAG &DAG,
@ -3622,7 +3574,6 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
case ISD::BR_CC: return LowerBR_CC(Op, DAG);
case ISD::BR_JT: return LowerBR_JT(Op, DAG);
case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
case ISD::VASTART: return LowerVASTART(Op, DAG);
case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
case ISD::SINT_TO_FP: