mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
When spilling an register, introduce a new temporary for each of its
spills. This allows for more flexibility when allocating registers for spill code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13907 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
25d4b54f93
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@ -80,9 +80,9 @@ namespace llvm {
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}
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}
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};
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};
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struct EndPointComp {
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struct StartPointPtrComp {
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bool operator()(const Interval& lhs, const Interval& rhs) {
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bool operator()(const Interval* lhs, const Interval* rhs) {
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return lhs.ranges.back().second < rhs.ranges.back().second;
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return lhs->ranges.front().first < rhs->ranges.front().first;
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}
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}
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};
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};
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@ -164,7 +164,9 @@ namespace llvm {
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Intervals& getIntervals() { return intervals_; }
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Intervals& getIntervals() { return intervals_; }
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void updateSpilledInterval(Interval& i, VirtRegMap& vrm, int slot);
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std::vector<Interval*> addIntervalsForSpills(const Interval& i,
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VirtRegMap& vrm,
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int slot);
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private:
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private:
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/// computeIntervals - compute live intervals
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/// computeIntervals - compute live intervals
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@ -186,19 +186,23 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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return true;
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return true;
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}
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}
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void LiveIntervals::updateSpilledInterval(Interval& li,
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std::vector<LiveIntervals::Interval*>
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LiveIntervals::addIntervalsForSpills(const Interval& li,
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VirtRegMap& vrm,
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VirtRegMap& vrm,
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int slot)
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int slot)
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{
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{
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std::vector<Interval*> added;
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assert(li.weight != HUGE_VAL &&
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assert(li.weight != HUGE_VAL &&
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"attempt to spill already spilled interval!");
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"attempt to spill already spilled interval!");
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Interval::Ranges oldRanges;
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swap(oldRanges, li.ranges);
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DEBUG(std::cerr << "\t\t\t\tupdating interval: " << li);
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DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: "
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<< li << '\n');
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for (Interval::Ranges::iterator i = oldRanges.begin(), e = oldRanges.end();
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const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
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i != e; ++i) {
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for (Interval::Ranges::const_iterator
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i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
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unsigned index = getBaseIndex(i->first);
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unsigned index = getBaseIndex(i->first);
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unsigned end = getBaseIndex(i->second-1) + InstrSlots::NUM;
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unsigned end = getBaseIndex(i->second-1) + InstrSlots::NUM;
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for (; index < end; index += InstrSlots::NUM) {
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for (; index < end; index += InstrSlots::NUM) {
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@ -240,16 +244,31 @@ void LiveIntervals::updateSpilledInterval(Interval& li,
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unsigned end = 1 + (mop.isDef() ?
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unsigned end = 1 + (mop.isDef() ?
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getUseIndex(index+InstrSlots::NUM) :
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getUseIndex(index+InstrSlots::NUM) :
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getUseIndex(index));
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getUseIndex(index));
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li.addRange(start, end);
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// create a new register for this spill
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unsigned nReg =
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mf_->getSSARegMap()->createVirtualRegister(rc);
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mi->SetMachineOperandReg(i, nReg);
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vrm.grow();
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vrm.assignVirt2StackSlot(nReg, slot);
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Interval& nI = getOrCreateInterval(nReg);
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assert(nI.empty());
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// the spill weight is now infinity as it
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// cannot be spilled again
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nI.weight = HUGE_VAL;
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nI.addRange(start, end);
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added.push_back(&nI);
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// update live variables
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lv_->addVirtualRegisterKilled(nReg, mi->getParent(),mi);
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DEBUG(std::cerr << "\t\t\t\tadded new interval: "
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<< nI << '\n');
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}
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}
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}
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}
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}
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}
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}
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}
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}
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}
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// the new spill weight is now infinity as it cannot be spilled again
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li.weight = HUGE_VAL;
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return added;
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DEBUG(std::cerr << '\n');
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DEBUG(std::cerr << "\t\t\t\tupdated interval: " << li << '\n');
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}
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}
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void LiveIntervals::printRegName(unsigned reg) const
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void LiveIntervals::printRegName(unsigned reg) const
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@ -80,9 +80,9 @@ namespace llvm {
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}
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}
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};
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};
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struct EndPointComp {
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struct StartPointPtrComp {
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bool operator()(const Interval& lhs, const Interval& rhs) {
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bool operator()(const Interval* lhs, const Interval* rhs) {
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return lhs.ranges.back().second < rhs.ranges.back().second;
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return lhs->ranges.front().first < rhs->ranges.front().first;
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}
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}
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};
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};
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@ -164,7 +164,9 @@ namespace llvm {
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Intervals& getIntervals() { return intervals_; }
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Intervals& getIntervals() { return intervals_; }
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void updateSpilledInterval(Interval& i, VirtRegMap& vrm, int slot);
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std::vector<Interval*> addIntervalsForSpills(const Interval& i,
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VirtRegMap& vrm,
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int slot);
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private:
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private:
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/// computeIntervals - compute live intervals
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/// computeIntervals - compute live intervals
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@ -27,6 +27,7 @@
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#include <algorithm>
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#include <algorithm>
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#include <cmath>
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#include <cmath>
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#include <iostream>
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#include <iostream>
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#include <set>
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using namespace llvm;
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using namespace llvm;
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@ -366,24 +367,26 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
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DEBUG(std::cerr << "\t\tregister with min weight: "
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DEBUG(std::cerr << "\t\tregister with min weight: "
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<< mri_->getName(minReg) << " (" << minWeight << ")\n");
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<< mri_->getName(minReg) << " (" << minWeight << ")\n");
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// if the current has the minimum weight, we need to modify it,
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// if the current has the minimum weight, we need to spill it and
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// push it back in unhandled and let the linear scan algorithm run
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// add any added intervals back to unhandled, and restart
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// again
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// linearscan.
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if (cur->weight <= minWeight) {
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if (cur->weight <= minWeight) {
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DEBUG(std::cerr << "\t\t\tspilling(c): " << *cur << '\n';);
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DEBUG(std::cerr << "\t\t\tspilling(c): " << *cur << '\n';);
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int slot = vrm_->assignVirt2StackSlot(cur->reg);
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int slot = vrm_->assignVirt2StackSlot(cur->reg);
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li_->updateSpilledInterval(*cur, *vrm_, slot);
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std::vector<LiveIntervals::Interval*> added =
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li_->addIntervalsForSpills(*cur, *vrm_, slot);
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// if we didn't eliminate the interval find where to add it
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// merge added with unhandled
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// back to unhandled. We need to scan since unhandled are
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std::vector<LiveIntervals::Interval*>::iterator addedIt = added.begin();
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// sorted on earliest start point and we may have changed our
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std::vector<LiveIntervals::Interval*>::iterator addedItEnd = added.end();
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// start point.
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for (IntervalPtrs::iterator i = unhandled_.begin(), e = unhandled_.end();
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if (!cur->empty()) {
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i != e && addedIt != addedItEnd; ++i) {
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IntervalPtrs::iterator it = unhandled_.begin();
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if ((*i)->start() > (*addedIt)->start())
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while (it != unhandled_.end() && (*it)->start() < cur->start())
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i = unhandled_.insert(i, *(addedIt++));
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++it;
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unhandled_.insert(it, cur);
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}
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}
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while (addedIt != addedItEnd)
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unhandled_.push_back(*(addedIt++));
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return;
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return;
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}
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}
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@ -395,6 +398,7 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
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// otherwise we spill all intervals aliasing the register with
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// otherwise we spill all intervals aliasing the register with
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// minimum weight, rollback to the interval with the earliest
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// minimum weight, rollback to the interval with the earliest
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// start point and let the linear scan algorithm run again
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// start point and let the linear scan algorithm run again
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std::vector<LiveIntervals::Interval*> added;
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assert(MRegisterInfo::isPhysicalRegister(minReg) &&
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assert(MRegisterInfo::isPhysicalRegister(minReg) &&
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"did not choose a register to spill?");
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"did not choose a register to spill?");
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std::vector<bool> toSpill(mri_->getNumRegs(), false);
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std::vector<bool> toSpill(mri_->getNumRegs(), false);
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@ -403,6 +407,8 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
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toSpill[*as] = true;
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toSpill[*as] = true;
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unsigned earliestStart = cur->start();
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unsigned earliestStart = cur->start();
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std::set<unsigned> spilled;
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for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
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for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
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unsigned reg = (*i)->reg;
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unsigned reg = (*i)->reg;
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if (MRegisterInfo::isVirtualRegister(reg) &&
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if (MRegisterInfo::isVirtualRegister(reg) &&
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@ -411,7 +417,10 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
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DEBUG(std::cerr << "\t\t\tspilling(a): " << **i << '\n');
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DEBUG(std::cerr << "\t\t\tspilling(a): " << **i << '\n');
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earliestStart = std::min(earliestStart, (*i)->start());
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earliestStart = std::min(earliestStart, (*i)->start());
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int slot = vrm_->assignVirt2StackSlot((*i)->reg);
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int slot = vrm_->assignVirt2StackSlot((*i)->reg);
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li_->updateSpilledInterval(**i, *vrm_, slot);
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std::vector<LiveIntervals::Interval*> newIs =
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li_->addIntervalsForSpills(**i, *vrm_, slot);
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std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
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spilled.insert(reg);
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}
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}
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}
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}
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for (IntervalPtrs::iterator i = inactive_.begin();
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for (IntervalPtrs::iterator i = inactive_.begin();
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@ -423,7 +432,10 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
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DEBUG(std::cerr << "\t\t\tspilling(i): " << **i << '\n');
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DEBUG(std::cerr << "\t\t\tspilling(i): " << **i << '\n');
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earliestStart = std::min(earliestStart, (*i)->start());
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earliestStart = std::min(earliestStart, (*i)->start());
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int slot = vrm_->assignVirt2StackSlot((*i)->reg);
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int slot = vrm_->assignVirt2StackSlot((*i)->reg);
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li_->updateSpilledInterval(**i, *vrm_, slot);
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std::vector<LiveIntervals::Interval*> newIs =
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li_->addIntervalsForSpills(**i, *vrm_, slot);
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std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
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spilled.insert(reg);
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}
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}
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}
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}
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@ -433,7 +445,7 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
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while (!handled_.empty()) {
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while (!handled_.empty()) {
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IntervalPtrs::value_type i = handled_.back();
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IntervalPtrs::value_type i = handled_.back();
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// if this interval starts before t we are done
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// if this interval starts before t we are done
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if (!i->empty() && i->start() < earliestStart)
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if (i->start() < earliestStart)
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break;
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break;
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DEBUG(std::cerr << "\t\t\tundo changes for: " << *i << '\n');
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DEBUG(std::cerr << "\t\t\tundo changes for: " << *i << '\n');
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handled_.pop_back();
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handled_.pop_back();
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@ -445,20 +457,10 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
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unhandled_.push_front(i);
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unhandled_.push_front(i);
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}
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}
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else {
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else {
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if (!spilled.count(i->reg))
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unhandled_.push_front(i);
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prt_->delRegUse(vrm_->getPhys(i->reg));
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prt_->delRegUse(vrm_->getPhys(i->reg));
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vrm_->clearVirt(i->reg);
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vrm_->clearVirt(i->reg);
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if (i->spilled()) {
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if (!i->empty()) {
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IntervalPtrs::iterator it = unhandled_.begin();
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while (it != unhandled_.end() &&
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(*it)->start() < i->start())
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++it;
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unhandled_.insert(it, i);
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}
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}
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else
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unhandled_.push_front(i);
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}
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}
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}
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}
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else if ((it = find(inactive_.begin(), inactive_.end(), i)) != inactive_.end()) {
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else if ((it = find(inactive_.begin(), inactive_.end(), i)) != inactive_.end()) {
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@ -466,18 +468,9 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
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if (MRegisterInfo::isPhysicalRegister(i->reg))
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if (MRegisterInfo::isPhysicalRegister(i->reg))
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unhandled_.push_front(i);
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unhandled_.push_front(i);
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else {
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else {
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vrm_->clearVirt(i->reg);
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if (!spilled.count(i->reg))
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if (i->spilled()) {
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if (!i->empty()) {
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IntervalPtrs::iterator it = unhandled_.begin();
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while (it != unhandled_.end() &&
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(*it)->start() < i->start())
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++it;
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unhandled_.insert(it, i);
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}
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}
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else
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unhandled_.push_front(i);
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unhandled_.push_front(i);
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vrm_->clearVirt(i->reg);
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}
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}
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}
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}
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else {
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else {
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prt_->addRegUse(vrm_->getPhys((*i)->reg));
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prt_->addRegUse(vrm_->getPhys((*i)->reg));
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}
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}
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}
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}
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std::sort(added.begin(), added.end(), LiveIntervals::StartPointPtrComp());
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// merge added with unhandled
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std::vector<LiveIntervals::Interval*>::iterator addedIt = added.begin();
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std::vector<LiveIntervals::Interval*>::iterator addedItEnd = added.end();
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for (IntervalPtrs::iterator i = unhandled_.begin(), e = unhandled_.end();
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i != e && addedIt != addedItEnd; ++i) {
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if ((*i)->start() > (*addedIt)->start())
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i = unhandled_.insert(i, *(addedIt++));
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}
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while (addedIt != addedItEnd)
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unhandled_.push_back(*(addedIt++));
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}
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}
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unsigned RA::getFreePhysReg(IntervalPtrs::value_type cur)
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unsigned RA::getFreePhysReg(IntervalPtrs::value_type cur)
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