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Revert r159938 (and r159945) to appease the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -567,8 +567,8 @@ def VMOVRRS : AVConv3I<0b11000101, 0b1010,
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bits<4> Rt2;
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// Encode instruction operands.
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let Inst{3-0} = src1{4-1};
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let Inst{5} = src1{0};
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let Inst{3-0} = src1{3-0};
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let Inst{5} = src1{4};
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let Inst{15-12} = Rt;
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let Inst{19-16} = Rt2;
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@ -617,8 +617,8 @@ def VMOVSRR : AVConv5I<0b11000100, 0b1010,
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bits<4> src2;
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// Encode instruction operands.
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let Inst{3-0} = dst1{4-1};
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let Inst{5} = dst1{0};
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let Inst{3-0} = dst1{3-0};
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let Inst{5} = dst1{4};
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let Inst{15-12} = src1;
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let Inst{19-16} = src2;
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@ -4198,9 +4198,9 @@ static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
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DecodeStatus S = MCDisassembler::Success;
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unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
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unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
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unsigned Rm = fieldFromInstruction32(Insn, 5, 1);
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unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
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unsigned pred = fieldFromInstruction32(Insn, 28, 4);
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Rm |= fieldFromInstruction32(Insn, 0, 4) << 4;
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Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
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if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
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S = MCDisassembler::SoftFail;
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@ -4224,9 +4224,9 @@ static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
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DecodeStatus S = MCDisassembler::Success;
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unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
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unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
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unsigned Rm = fieldFromInstruction32(Insn, 5, 1);
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unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
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unsigned pred = fieldFromInstruction32(Insn, 28, 4);
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Rm |= fieldFromInstruction32(Insn, 0, 4) << 1;
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Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
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if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
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S = MCDisassembler::SoftFail;
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@ -196,27 +196,6 @@
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@ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec]
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vmov r0, r1, d16
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@ Between two single precision registers and two core registers
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vmov s3, s4, r1, r2
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vmov s2, s3, r1, r2
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vmov r1, r2, s3, s4
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vmov r1, r2, s2, s3
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@ CHECK: vmov s3, s4, r1, r2 @ encoding: [0x31,0x1a,0x42,0xec]
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@ CHECK: vmov s2, s3, r1, r2 @ encoding: [0x11,0x1a,0x42,0xec]
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@ CHECK: vmov r1, r2, s3, s4 @ encoding: [0x31,0x1a,0x52,0xec]
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@ CHECK: vmov r1, r2, s2, s3 @ encoding: [0x11,0x1a,0x52,0xec]
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@ Between one double precision register and two core registers
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vmov d15, r1, r2
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vmov d16, r1, r2
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vmov r1, r2, d15
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vmov r1, r2, d16
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@ CHECK: vmov d15, r1, r2 @ encoding: [0x1f,0x1b,0x42,0xec]
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@ CHECK: vmov d16, r1, r2 @ encoding: [0x30,0x1b,0x42,0xec]
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@ CHECK: vmov r1, r2, d15 @ encoding: [0x1f,0x1b,0x52,0xec]
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@ CHECK: vmov r1, r2, d16 @ encoding: [0x30,0x1b,0x52,0xec]
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@ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed]
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@ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed]
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@ CHECK: vldr d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed]
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