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https://github.com/c64scene-ar/llvm-6502.git
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Refactor to parameterize some ARM load/store encoding patterns. Preparatory
to splitting the load/store pre/post indexed instructions into [r, r] and [r, imm] forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118925 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
5de6d841a5
commit
2716e25c2c
@ -491,90 +491,28 @@ class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
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let Inst{27-26} = 0b01;
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}
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// Pre-indexed loads
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class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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// Pre-indexed load/stores
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class AI2ldstpr<bit isLd, bit opc22, dag oops, dag iops, Format f,
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InstrItinClass itin, string opc, string asm, string cstr,
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list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
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opc, asm, cstr, pattern> {
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let Inst{20} = 1; // L bit
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let Inst{20} = isLd; // L bit
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let Inst{21} = 1; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = 0b01;
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}
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class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
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opc, asm, cstr, pattern> {
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let Inst{20} = 1; // L bit
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let Inst{21} = 1; // W bit
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let Inst{22} = 1; // B bit
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let Inst{22} = opc22; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = 0b01;
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}
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// Pre-indexed stores
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class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
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opc, asm, cstr, pattern> {
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let Inst{20} = 0; // L bit
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let Inst{21} = 1; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = 0b01;
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}
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class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
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opc, asm, cstr, pattern> {
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let Inst{20} = 0; // L bit
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let Inst{21} = 1; // W bit
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let Inst{22} = 1; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = 0b01;
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}
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// Post-indexed loads
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class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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// Post-indexed load/stores
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class AI2ldstpo<bit isLd, bit opc22, dag oops, dag iops, Format f,
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InstrItinClass itin, string opc, string asm, string cstr,
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list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
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opc, asm, cstr,pattern> {
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let Inst{20} = 1; // L bit
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let Inst{20} = isLd; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 0; // P bit
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let Inst{27-26} = 0b01;
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}
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class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
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opc, asm, cstr,pattern> {
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 1; // B bit
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let Inst{24} = 0; // P bit
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let Inst{27-26} = 0b01;
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}
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// Post-indexed stores
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class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
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opc, asm, cstr,pattern> {
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let Inst{20} = 0; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 0; // P bit
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let Inst{27-26} = 0b01;
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}
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class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
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opc, asm, cstr,pattern> {
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let Inst{20} = 0; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 1; // B bit
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let Inst{22} = opc22; // B bit
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let Inst{24} = 0; // P bit
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let Inst{27-26} = 0b01;
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}
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@ -1540,11 +1540,11 @@ def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
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[]>, Requires<[IsARM, HasV5TE]>;
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// Indexed loads
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def LDR_PRE : AI2ldwpr<(outs GPR:$Rt, GPR:$Rn_wb),
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def LDR_PRE : AI2ldstpr<1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins addrmode2:$addr), LdFrm, IIC_iLoad_ru,
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"ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
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def LDR_POST : AI2ldwpo<(outs GPR:$Rt, GPR:$Rn_wb),
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def LDR_POST : AI2ldstpo<1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn, am2offset:$offset), LdFrm, IIC_iLoad_ru,
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"ldr", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
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@ -1556,11 +1556,11 @@ def LDRH_POST : AI3ldhpo<(outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
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"ldrh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
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def LDRB_PRE : AI2ldbpr<(outs GPR:$Rt, GPR:$Rn_wb),
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def LDRB_PRE : AI2ldstpr<1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru,
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"ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
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def LDRB_POST : AI2ldbpo<(outs GPR:$Rt, GPR:$Rn_wb),
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def LDRB_POST : AI2ldstpo<1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
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"ldrb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
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@ -1596,13 +1596,13 @@ def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
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// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
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def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
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def LDRT : AI2ldstpo<1, 0, (outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
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"ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
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let Inst{21} = 1; // overwrite
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}
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def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
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def LDRBT : AI2ldstpo<1, 1, (outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
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"ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
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let Inst{21} = 1; // overwrite
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@ -1641,14 +1641,14 @@ def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
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"strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
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// Indexed stores
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def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
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def STR_PRE : AI2ldstpr<0, 0, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base, am2offset:$offset),
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StFrm, IIC_iStore_ru,
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"str", "\t$src, [$base, $offset]!", "$base = $base_wb",
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[(set GPR:$base_wb,
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(pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
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def STR_POST : AI2stwpo<(outs GPR:$base_wb),
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def STR_POST : AI2ldstpo<0, 0, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset),
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StFrm, IIC_iStore_ru,
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"str", "\t$src, [$base], $offset", "$base = $base_wb",
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@ -1669,14 +1669,14 @@ def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
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[(set GPR:$base_wb, (post_truncsti16 GPR:$src,
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GPR:$base, am3offset:$offset))]>;
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def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
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def STRB_PRE : AI2ldstpr<0, 1, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset),
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StFrm, IIC_iStore_bh_ru,
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"strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
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[(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
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GPR:$base, am2offset:$offset))]>;
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def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
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def STRB_POST: AI2ldstpo<0, 1, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset),
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StFrm, IIC_iStore_bh_ru,
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"strb", "\t$src, [$base], $offset", "$base = $base_wb",
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@ -1699,7 +1699,7 @@ def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
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// STRT, STRBT, and STRHT are for disassembly only.
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def STRT : AI2stwpo<(outs GPR:$base_wb),
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def STRT : AI2ldstpo<0, 0, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset),
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StFrm, IIC_iStore_ru,
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"strt", "\t$src, [$base], $offset", "$base = $base_wb",
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@ -1707,7 +1707,7 @@ def STRT : AI2stwpo<(outs GPR:$base_wb),
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let Inst{21} = 1; // overwrite
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}
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def STRBT : AI2stbpo<(outs GPR:$base_wb),
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def STRBT : AI2ldstpo<0, 1, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset),
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StFrm, IIC_iStore_bh_ru,
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"strbt", "\t$src, [$base], $offset", "$base = $base_wb",
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