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Refactor to parameterize some ARM load/store encoding patterns. Preparatory

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to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118925 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-11-12 21:28:15 +00:00
parent 5de6d841a5
commit 2716e25c2c
2 changed files with 24 additions and 86 deletions
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86
lib/Target/ARM/ARMInstrFormats.td
View File

@ -491,90 +491,28 @@ class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{27-26} = 0b01; let Inst{27-26} = 0b01;
} }
// Pre-indexed loads // Pre-indexed load/stores
class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin, class AI2ldstpr<bit isLd, bit opc22, dag oops, dag iops, Format f,
string opc, string asm, string cstr, list<dag> pattern> InstrItinClass itin, string opc, string asm, string cstr,
list<dag> pattern>
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
opc, asm, cstr, pattern> { opc, asm, cstr, pattern> {
let Inst{20} = 1; // L bit let Inst{20} = isLd; // L bit
let Inst{21} = 1; // W bit let Inst{21} = 1; // W bit
let Inst{22} = 0; // B bit let Inst{22} = opc22; // B bit
let Inst{24} = 1; // P bit
let Inst{27-26} = 0b01;
}
class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern>
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
opc, asm, cstr, pattern> {
let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = 0b01; let Inst{27-26} = 0b01;
} }
// Pre-indexed stores // Post-indexed load/stores
class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin, class AI2ldstpo<bit isLd, bit opc22, dag oops, dag iops, Format f,
string opc, string asm, string cstr, list<dag> pattern> InstrItinClass itin, string opc, string asm, string cstr,
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, list<dag> pattern>
opc, asm, cstr, pattern> {
let Inst{20} = 0; // L bit
let Inst{21} = 1; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
let Inst{27-26} = 0b01;
}
class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern>
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
opc, asm, cstr, pattern> {
let Inst{20} = 0; // L bit
let Inst{21} = 1; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
let Inst{27-26} = 0b01;
}
// Post-indexed loads
class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern>
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
opc, asm, cstr,pattern> { opc, asm, cstr,pattern> {
let Inst{20} = 1; // L bit let Inst{20} = isLd; // L bit
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit let Inst{22} = opc22; // B bit
let Inst{24} = 0; // P bit
let Inst{27-26} = 0b01;
}
class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern>
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
opc, asm, cstr,pattern> {
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 0; // P bit
let Inst{27-26} = 0b01;
}
// Post-indexed stores
class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern>
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
opc, asm, cstr,pattern> {
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 0; // P bit
let Inst{27-26} = 0b01;
}
class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern>
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
opc, asm, cstr,pattern> {
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 0; // P bit let Inst{24} = 0; // P bit
let Inst{27-26} = 0b01; let Inst{27-26} = 0b01;
} }

24
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1540,11 +1540,11 @@ def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
[]>, Requires<[IsARM, HasV5TE]>; []>, Requires<[IsARM, HasV5TE]>;
// Indexed loads // Indexed loads
def LDR_PRE : AI2ldwpr<(outs GPR:$Rt, GPR:$Rn_wb), def LDR_PRE : AI2ldstpr<1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addrmode2:$addr), LdFrm, IIC_iLoad_ru, (ins addrmode2:$addr), LdFrm, IIC_iLoad_ru,
"ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>; "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
def LDR_POST : AI2ldwpo<(outs GPR:$Rt, GPR:$Rn_wb), def LDR_POST : AI2ldstpo<1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins GPR:$Rn, am2offset:$offset), LdFrm, IIC_iLoad_ru, (ins GPR:$Rn, am2offset:$offset), LdFrm, IIC_iLoad_ru,
"ldr", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>; "ldr", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
@ -1556,11 +1556,11 @@ def LDRH_POST : AI3ldhpo<(outs GPR:$Rt, GPR:$Rn_wb),
(ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, (ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
"ldrh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>; "ldrh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
def LDRB_PRE : AI2ldbpr<(outs GPR:$Rt, GPR:$Rn_wb), def LDRB_PRE : AI2ldstpr<1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru, (ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru,
"ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>; "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
def LDRB_POST : AI2ldbpo<(outs GPR:$Rt, GPR:$Rn_wb), def LDRB_POST : AI2ldstpo<1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins GPR:$Rn,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru, (ins GPR:$Rn,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
"ldrb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>; "ldrb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
@ -1596,13 +1596,13 @@ def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only. // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), def LDRT : AI2ldstpo<1, 0, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru, (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
"ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> { "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
let Inst{21} = 1; // overwrite let Inst{21} = 1; // overwrite
} }
def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), def LDRBT : AI2ldstpo<1, 1, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru, (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
"ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> { "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
let Inst{21} = 1; // overwrite let Inst{21} = 1; // overwrite
@ -1641,14 +1641,14 @@ def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
"strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>; "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
// Indexed stores // Indexed stores
def STR_PRE : AI2stwpr<(outs GPR:$base_wb), def STR_PRE : AI2ldstpr<0, 0, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, am2offset:$offset), (ins GPR:$src, GPR:$base, am2offset:$offset),
StFrm, IIC_iStore_ru, StFrm, IIC_iStore_ru,
"str", "\t$src, [$base, $offset]!", "$base = $base_wb", "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb, [(set GPR:$base_wb,
(pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
def STR_POST : AI2stwpo<(outs GPR:$base_wb), def STR_POST : AI2ldstpo<0, 0, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset), (ins GPR:$src, GPR:$base,am2offset:$offset),
StFrm, IIC_iStore_ru, StFrm, IIC_iStore_ru,
"str", "\t$src, [$base], $offset", "$base = $base_wb", "str", "\t$src, [$base], $offset", "$base = $base_wb",
@ -1669,14 +1669,14 @@ def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
[(set GPR:$base_wb, (post_truncsti16 GPR:$src, [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
GPR:$base, am3offset:$offset))]>; GPR:$base, am3offset:$offset))]>;
def STRB_PRE : AI2stbpr<(outs GPR:$base_wb), def STRB_PRE : AI2ldstpr<0, 1, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset), (ins GPR:$src, GPR:$base,am2offset:$offset),
StFrm, IIC_iStore_bh_ru, StFrm, IIC_iStore_bh_ru,
"strb", "\t$src, [$base, $offset]!", "$base = $base_wb", "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb, (pre_truncsti8 GPR:$src, [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
GPR:$base, am2offset:$offset))]>; GPR:$base, am2offset:$offset))]>;
def STRB_POST: AI2stbpo<(outs GPR:$base_wb), def STRB_POST: AI2ldstpo<0, 1, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset), (ins GPR:$src, GPR:$base,am2offset:$offset),
StFrm, IIC_iStore_bh_ru, StFrm, IIC_iStore_bh_ru,
"strb", "\t$src, [$base], $offset", "$base = $base_wb", "strb", "\t$src, [$base], $offset", "$base = $base_wb",
@ -1699,7 +1699,7 @@ def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
// STRT, STRBT, and STRHT are for disassembly only. // STRT, STRBT, and STRHT are for disassembly only.
def STRT : AI2stwpo<(outs GPR:$base_wb), def STRT : AI2ldstpo<0, 0, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset), (ins GPR:$src, GPR:$base,am2offset:$offset),
StFrm, IIC_iStore_ru, StFrm, IIC_iStore_ru,
"strt", "\t$src, [$base], $offset", "$base = $base_wb", "strt", "\t$src, [$base], $offset", "$base = $base_wb",
@ -1707,7 +1707,7 @@ def STRT : AI2stwpo<(outs GPR:$base_wb),
let Inst{21} = 1; // overwrite let Inst{21} = 1; // overwrite
} }
def STRBT : AI2stbpo<(outs GPR:$base_wb), def STRBT : AI2ldstpo<0, 1, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset), (ins GPR:$src, GPR:$base,am2offset:$offset),
StFrm, IIC_iStore_bh_ru, StFrm, IIC_iStore_bh_ru,
"strbt", "\t$src, [$base], $offset", "$base = $base_wb", "strbt", "\t$src, [$base], $offset", "$base = $base_wb",