6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 04:30:12 +00:00
Code Issues Projects Releases Wiki Activity

Currently we cannot handle two-address instructions of the form:

Browse Source 
A = B op C where A == C, but this cannot really occur in practice
because of SSA form. Add an assert to check that just to be safe.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10682 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos 2004-01-05 02:25:45 +00:00
parent 50c047d159
commit 271bd2d7f1
1 changed files with 9 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -123,6 +123,15 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &fn) {
bool regAisPhysical = regA < MRegisterInfo::FirstVirtualRegister;
bool regBisPhysical = regB < MRegisterInfo::FirstVirtualRegister;
// first make sure we do not have a use of a in the
// instruction (a = b + a for example) because our
// transofrmation will not work. This should never occur
// because of SSA.
for (unsigned i = 1; i < mi->getNumOperands(); ++i) {
assert(!mi->getOperand(i).isRegister() ||
mi->getOperand(i).getAllocatedRegNum() != regA);
}
const TargetRegisterClass* rc = regAisPhysical ?
mri_->getRegClass(regA) :
mf_->getSSARegMap()->getRegClass(regA);