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R600: Don't emit empty then clause and use alu_pop_after
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186725 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune
parent
12140450fa
commit
272458bd06
@ -1039,8 +1039,11 @@ int AMDGPUCFGStructurizer::ifPatternMatch(MachineBasicBlock *MBB) {
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} else if (FalseMBB->succ_size() == 1
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&& *FalseMBB->succ_begin() == TrueMBB) {
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// Triangle pattern, true is empty
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LandBlk = TrueMBB;
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TrueMBB = NULL;
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// We reverse the predicate to make a triangle, empty false pattern;
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std::swap(TrueMBB, FalseMBB);
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reversePredicateSetter(MBB->end());
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LandBlk = FalseMBB;
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FalseMBB = NULL;
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} else if (FalseMBB->succ_size() == 1
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&& isSameloopDetachedContbreak(TrueMBB, FalseMBB)) {
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LandBlk = *FalseMBB->succ_begin();
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@ -1456,6 +1459,7 @@ void AMDGPUCFGStructurizer::mergeSerialBlock(MachineBasicBlock *DstMBB,
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void AMDGPUCFGStructurizer::mergeIfthenelseBlock(MachineInstr *BranchMI,
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MachineBasicBlock *MBB, MachineBasicBlock *TrueMBB,
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MachineBasicBlock *FalseMBB, MachineBasicBlock *LandMBB) {
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assert (TrueMBB);
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DEBUG(
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dbgs() << "ifPattern BB" << MBB->getNumber();
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dbgs() << "{ ";
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@ -347,6 +347,9 @@ public:
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MaxStack = 1;
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}
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std::vector<ClauseFile> FetchClauses, AluClauses;
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std::vector<MachineInstr *> LastAlu(1);
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std::vector<MachineInstr *> ToPopAfter;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E;) {
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if (TII->usesTextureCache(I) || TII->usesVertexCache(I)) {
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@ -357,6 +360,10 @@ public:
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}
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MachineBasicBlock::iterator MI = I;
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if (MI->getOpcode() != AMDGPU::ENDIF)
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LastAlu.back() = 0;
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if (MI->getOpcode() == AMDGPU::CF_ALU)
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LastAlu.back() = MI;
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I++;
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switch (MI->getOpcode()) {
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case AMDGPU::CF_ALU_PUSH_BEFORE:
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@ -403,6 +410,7 @@ public:
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break;
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}
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case AMDGPU::IF_PREDICATE_SET: {
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LastAlu.push_back(0);
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MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
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getHWInstrDesc(CF_JUMP))
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.addImm(0)
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@ -420,7 +428,7 @@ public:
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MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
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getHWInstrDesc(CF_ELSE))
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.addImm(0)
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.addImm(1);
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.addImm(0);
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DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
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IfThenElseStack.push_back(MIb);
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MI->eraseFromParent();
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@ -429,17 +437,24 @@ public:
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}
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case AMDGPU::ENDIF: {
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CurrentStack--;
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MachineInstr *IfOrElseInst = IfThenElseStack.back();
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IfThenElseStack.pop_back();
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CounterPropagateAddr(IfOrElseInst, CfCount + 1);
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if (LastAlu.back()) {
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ToPopAfter.push_back(LastAlu.back());
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} else {
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MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
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getHWInstrDesc(CF_POP))
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.addImm(CfCount + 1)
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.addImm(1);
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(void)MIb;
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DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
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MI->eraseFromParent();
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CfCount++;
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}
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MachineInstr *IfOrElseInst = IfThenElseStack.back();
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IfThenElseStack.pop_back();
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CounterPropagateAddr(IfOrElseInst, CfCount);
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IfOrElseInst->getOperand(1).setImm(1);
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LastAlu.pop_back();
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MI->eraseFromParent();
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break;
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}
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case AMDGPU::PREDICATED_BREAK: {
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@ -484,6 +499,21 @@ public:
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break;
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}
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}
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for (unsigned i = 0, e = ToPopAfter.size(); i < e; ++i) {
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MachineInstr *Alu = ToPopAfter[i];
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BuildMI(MBB, Alu, MBB.findDebugLoc((MachineBasicBlock::iterator)Alu),
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TII->get(AMDGPU::CF_ALU_POP_AFTER))
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.addImm(Alu->getOperand(0).getImm())
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.addImm(Alu->getOperand(1).getImm())
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.addImm(Alu->getOperand(2).getImm())
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.addImm(Alu->getOperand(3).getImm())
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.addImm(Alu->getOperand(4).getImm())
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.addImm(Alu->getOperand(5).getImm())
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.addImm(Alu->getOperand(6).getImm())
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.addImm(Alu->getOperand(7).getImm())
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.addImm(Alu->getOperand(8).getImm());
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Alu->eraseFromParent();
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}
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MFI->StackSize = getHWStackSize(MaxStack, HasPush);
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}
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@ -624,6 +624,7 @@ ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG {
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def CF_ALU : ALU_CLAUSE<8, "ALU">;
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def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
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def CF_ALU_POP_AFTER : ALU_CLAUSE<10, "ALU_POP_AFTER">;
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def FETCH_CLAUSE : AMDGPUInst <(outs),
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(ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {
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@ -1,6 +1,6 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; CHECK: JUMP @7
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; CHECK: JUMP @5
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; CHECK: EXPORT
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; CHECK-NOT: EXPORT
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@ -2,12 +2,11 @@
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;CHECK: TEX
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;CHECK: ALU_PUSH
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;CHECK: JUMP @4
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;CHECK: ELSE @16
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;CHECK: JUMP @15
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;CHECK: TEX
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;CHECK: LOOP_START_DX10 @15
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;CHECK: LOOP_BREAK @14
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;CHECK: POP @16
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;CHECK: LOOP_START_DX10 @14
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;CHECK: LOOP_BREAK @13
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;CHECK: POP @15
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64"
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target triple = "r600--"
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124
test/CodeGen/R600/r600cfg.ll
Normal file
124
test/CodeGen/R600/r600cfg.ll
Normal file
@ -0,0 +1,124 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood
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;REQUIRES: asserts
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define void @main() #0 {
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main_body:
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%0 = call float @llvm.R600.load.input(i32 4)
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%1 = call float @llvm.R600.load.input(i32 5)
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%2 = call float @llvm.R600.load.input(i32 6)
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%3 = call float @llvm.R600.load.input(i32 7)
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%4 = bitcast float %0 to i32
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%5 = icmp eq i32 %4, 0
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%6 = sext i1 %5 to i32
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%7 = bitcast i32 %6 to float
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%8 = bitcast float %7 to i32
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%9 = icmp ne i32 %8, 0
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%. = select i1 %9, float 0x36A0000000000000, float %0
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br label %LOOP
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LOOP: ; preds = %LOOP47, %main_body
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%temp12.0 = phi float [ 0x36A0000000000000, %main_body ], [ %temp12.1, %LOOP47 ]
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%temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %38, %LOOP47 ]
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%temp4.1 = phi float [ %., %main_body ], [ %52, %LOOP47 ]
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%10 = bitcast float %temp4.1 to i32
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%11 = icmp eq i32 %10, 1
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%12 = sext i1 %11 to i32
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%13 = bitcast i32 %12 to float
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%14 = bitcast float %13 to i32
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%15 = icmp ne i32 %14, 0
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br i1 %15, label %IF41, label %ENDIF40
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IF41: ; preds = %LOOP
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%16 = insertelement <4 x float> undef, float %0, i32 0
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%17 = insertelement <4 x float> %16, float %temp8.0, i32 1
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%18 = insertelement <4 x float> %17, float %temp12.0, i32 2
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%19 = insertelement <4 x float> %18, float 0.000000e+00, i32 3
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call void @llvm.R600.store.stream.output(<4 x float> %19, i32 0, i32 0, i32 1)
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%20 = insertelement <4 x float> undef, float %0, i32 0
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%21 = insertelement <4 x float> %20, float %temp8.0, i32 1
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%22 = insertelement <4 x float> %21, float %temp12.0, i32 2
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%23 = insertelement <4 x float> %22, float 0.000000e+00, i32 3
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call void @llvm.R600.store.stream.output(<4 x float> %23, i32 0, i32 0, i32 2)
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%24 = insertelement <4 x float> undef, float %0, i32 0
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%25 = insertelement <4 x float> %24, float %temp8.0, i32 1
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%26 = insertelement <4 x float> %25, float %temp12.0, i32 2
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%27 = insertelement <4 x float> %26, float 0.000000e+00, i32 3
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call void @llvm.R600.store.stream.output(<4 x float> %27, i32 0, i32 0, i32 4)
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%28 = insertelement <4 x float> undef, float 0.000000e+00, i32 0
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%29 = insertelement <4 x float> %28, float 0.000000e+00, i32 1
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%30 = insertelement <4 x float> %29, float 0.000000e+00, i32 2
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%31 = insertelement <4 x float> %30, float 0.000000e+00, i32 3
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call void @llvm.R600.store.swizzle(<4 x float> %31, i32 60, i32 1)
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%32 = insertelement <4 x float> undef, float %0, i32 0
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%33 = insertelement <4 x float> %32, float %temp8.0, i32 1
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%34 = insertelement <4 x float> %33, float %temp12.0, i32 2
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%35 = insertelement <4 x float> %34, float 0.000000e+00, i32 3
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call void @llvm.R600.store.swizzle(<4 x float> %35, i32 0, i32 2)
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ret void
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ENDIF40: ; preds = %LOOP
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%36 = bitcast float %temp8.0 to i32
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%37 = add i32 %36, 1
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%38 = bitcast i32 %37 to float
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%39 = bitcast float %temp4.1 to i32
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%40 = urem i32 %39, 2
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%41 = bitcast i32 %40 to float
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%42 = bitcast float %41 to i32
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%43 = icmp eq i32 %42, 0
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%44 = sext i1 %43 to i32
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%45 = bitcast i32 %44 to float
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%46 = bitcast float %45 to i32
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%47 = icmp ne i32 %46, 0
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%48 = bitcast float %temp4.1 to i32
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br i1 %47, label %IF44, label %ELSE45
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IF44: ; preds = %ENDIF40
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%49 = udiv i32 %48, 2
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br label %ENDIF43
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ELSE45: ; preds = %ENDIF40
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%50 = mul i32 3, %48
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%51 = add i32 %50, 1
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br label %ENDIF43
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ENDIF43: ; preds = %ELSE45, %IF44
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%.sink = phi i32 [ %49, %IF44 ], [ %51, %ELSE45 ]
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%52 = bitcast i32 %.sink to float
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%53 = load <4 x float> addrspace(8)* null
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%54 = extractelement <4 x float> %53, i32 0
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%55 = bitcast float %54 to i32
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br label %LOOP47
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LOOP47: ; preds = %ENDIF48, %ENDIF43
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%temp12.1 = phi float [ %temp12.0, %ENDIF43 ], [ %67, %ENDIF48 ]
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%temp28.0 = phi float [ 0.000000e+00, %ENDIF43 ], [ %70, %ENDIF48 ]
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%56 = bitcast float %temp28.0 to i32
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%57 = icmp uge i32 %56, %55
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%58 = sext i1 %57 to i32
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%59 = bitcast i32 %58 to float
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%60 = bitcast float %59 to i32
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%61 = icmp ne i32 %60, 0
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br i1 %61, label %LOOP, label %ENDIF48
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ENDIF48: ; preds = %LOOP47
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%62 = bitcast float %temp12.1 to i32
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%63 = mul i32 %62, 2
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%64 = bitcast i32 %63 to float
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%65 = bitcast float %64 to i32
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%66 = urem i32 %65, 2147483647
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%67 = bitcast i32 %66 to float
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%68 = bitcast float %temp28.0 to i32
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%69 = add i32 %68, 1
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%70 = bitcast i32 %69 to float
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br label %LOOP47
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}
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; Function Attrs: readnone
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declare float @llvm.R600.load.input(i32) #1
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declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32)
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declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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attributes #0 = { "ShaderType"="1" }
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attributes #1 = { readnone }
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