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https://github.com/c64scene-ar/llvm-6502.git
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add shladd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24080 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -15,6 +15,7 @@
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include "IA64InstrFormats.td"
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def u2imm : Operand<i8>;
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def u6imm : Operand<i8>;
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def s8imm : Operand<i8> {
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let PrintMethod = "printS8ImmOperand";
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@ -41,6 +42,21 @@ let PrintMethod = "printCallOperand" in
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/* new daggy action!!! */
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def is32ones : PatLeaf<(i64 imm), [{
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// is32ones predicate - True if the immediate is 0x00000000FFFFFFFF
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// Used to create ZXT4s appropriately
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int64_t v = (int64_t)N->getValue();
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return (v == 0x00000000FFFFFFFFLL);
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}]>;
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def isSHLADDimm: PatLeaf<(i64 imm), [{
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// isSHLADDimm predicate - True if the immediate is exactly 1, 2, 3 or 4
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// - 0 is *not* okay.
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// Used to create shladd instructions appropriately
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int64_t v = (int64_t)N->getValue();
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return (v >= 1 && v <= 4);
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}]>;
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def immSExt14 : PatLeaf<(i64 imm), [{
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// immSExt14 predicate - True if the immediate fits in a 14-bit sign extended
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// field. Used by instructions like 'adds'.
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@ -54,6 +70,19 @@ def imm64 : PatLeaf<(i64 imm), [{
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return true;
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}]>;
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def SXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt1 $dst = $src;;",
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[(set GR:$dst, (sext_inreg GR:$src, i8))]>;
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def ZXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt1 $dst = $src;;",
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[(set GR:$dst, (and GR:$src, 255))]>;
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def SXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt2 $dst = $src;;",
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[(set GR:$dst, (sext_inreg GR:$src, i16))]>;
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def ZXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt2 $dst = $src;;",
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[(set GR:$dst, (and GR:$src, 65535))]>;
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def SXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt4 $dst = $src;;",
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[(set GR:$dst, (sext_inreg GR:$src, i32))]>;
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def ZXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src;;",
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[(set GR:$dst, (and GR:$src, is32ones))]>;
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def ADD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"add $dst = $src1, $src2;;",
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[(set GR:$dst, (add GR:$src1, GR:$src2))]>;
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@ -107,6 +136,7 @@ def : Pat<(mul GR:$src1, GR:$src2),
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// load constants of various sizes // FIXME: prettyprint -ve constants
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def : Pat<(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm)>;
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def : Pat<(i64 imm64:$imm), (MOVL imm64:$imm)>;
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// TODO: def : Pat<(i1 1), (MOV p0)>;
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def AND : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"and $dst = $src1, $src2;;",
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@ -159,10 +189,22 @@ def XOR : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"xor $dst = $src1, $src2;;",
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[(set GR:$dst, (xor GR:$src1, GR:$src2))]>;
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def SHLADD: AForm_DAG<0x03, 0x0b, (ops GR:$dst,GR:$src1,s64imm:$imm,GR:$src2),
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"shladd $dst = $src1, $imm, $src2;;",
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[(set GR:$dst, (add GR:$src2, (shl GR:$src1, isSHLADDimm:$imm)))]>;
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def SHL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"shl $dst = $src1, $src2;;",
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[(set GR:$dst, (shl GR:$src1, GR:$src2))]>;
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def SHRU : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"shr.u $dst = $src1, $src2;;",
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[(set GR:$dst, (srl GR:$src1, GR:$src2))]>;
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def SHRS : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"shr $dst = $src1, $src2;;",
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[(set GR:$dst, (sra GR:$src1, GR:$src2))]>;
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/*
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def CMPEQ : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
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"cmp.eq $dst, p0 = $src1, $src2;;">;
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@ -219,22 +261,6 @@ def CMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
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"cmp.eq $dst, p0 = $src1, $src2;;",
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[(set PR:$dst, (setuge GR:$src1, GR:$src2))]>;
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// FIXME: tabelgen doesn't know that zxt1 is cheaper on ia64 than "andi",
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// need to fix this one day
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def SXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt1 $dst = $src;;",
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[(set GR:$dst, (sext_inreg GR:$src, i8))]>;
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def ZXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt1 $dst = $src;;",
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[(set GR:$dst, (and GR:$src, 255))]>;
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def SXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt2 $dst = $src;;",
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[(set GR:$dst, (sext_inreg GR:$src, i16))]>;
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def ZXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt2 $dst = $src;;",
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[(set GR:$dst, (and GR:$src, 65535))]>;
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def SXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt4 $dst = $src;;",
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[(set GR:$dst, (sext_inreg GR:$src, i32))]>;
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def ZXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src;;",
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[(set GR:$dst, (and GR:$src, 1341835918))]>; // hehhehe NO - FIXME
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// TODO: support postincrement (reg, imm9) loads+stores - this needs more
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// tablegen support
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@ -298,44 +324,18 @@ def MOVSIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, s22imm:$imm),
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def MOVLIMM64 : AForm<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
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"movl $dst = $imm;;">;
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/*
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def AND : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"and $dst = $src1, $src2;;">;
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def OR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"or $dst = $src1, $src2;;">;
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def XOR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"xor $dst = $src1, $src2;;">;
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def SHL : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"shl $dst = $src1, $src2;;">;
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*/
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def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
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"shl $dst = $src1, $imm;;">;
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def SHRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"shr.u $dst = $src1, $src2;;">;
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def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
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"shr.u $dst = $src1, $imm;;">;
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def SHRS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"shr $dst = $src1, $src2;;">;
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def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
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"shr $dst = $src1, $imm;;">;
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def SHLADD : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm, GR:$src2),
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"shladd $dst = $src1, $imm, $src2;;">;
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def EXTRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
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"extr.u $dst = $src1, $imm1, $imm2;;">;
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def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2;;">;
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/*
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def SXT1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt1 $dst = $src;;">;
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def ZXT1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt1 $dst = $src;;">;
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def SXT2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt2 $dst = $src;;">;
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def ZXT2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt2 $dst = $src;;">;
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def SXT4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt4 $dst = $src;;">;
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def ZXT4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src;;">;
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*/
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// and we do the whole thing again for FP compares!
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def FCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
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"fcmp.eq $dst, p0 = $src1, $src2;;">;
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