diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index a4ee0325138..ccb84ab82c3 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -5216,7 +5216,7 @@ struct AddSubFlagsOpcodePair {
   unsigned MachineOpc;
 };
 
-static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
+static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
   {ARM::ADCSri, ARM::ADCri},
   {ARM::ADCSrr, ARM::ADCrr},
   {ARM::ADCSrsi, ARM::ADCrsi},
@@ -5256,7 +5256,7 @@ bool ARMTargetLowering::RemapAddSubWithFlags(MachineInstr *MI,
   // the tiny opcode table is not costly.
   static const int NPairs =
     sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
-  for (AddSubFlagsOpcodePair *Pair = &AddSubFlagsOpcodeMap[0],
+  for (const AddSubFlagsOpcodePair *Pair = &AddSubFlagsOpcodeMap[0],
          *End = &AddSubFlagsOpcodeMap[NPairs]; Pair != End; ++Pair) {
     if (OldOpc == Pair->PseudoOpc) {
       NewOpc = Pair->MachineOpc;
@@ -5303,7 +5303,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
       Offset = -Offset;
 
     MachineMemOperand *MMO = *MI->memoperands_begin();
-    MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc))
+    BuildMI(*BB, MI, dl, TII->get(NewOpc))
       .addOperand(MI->getOperand(0))  // Rn_wb
       .addOperand(MI->getOperand(1))  // Rt
       .addOperand(MI->getOperand(2))  // Rn
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 98181b580ec..9c940c49ca3 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -10345,9 +10345,8 @@ static void ReplaceATOMIC_LOAD(SDNode *Node,
   // FIXME: On 32-bit, load -> fild or movq would be more efficient
   //        (The only way to get a 16-byte load is cmpxchg16b)
   // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
-  SDValue Zero = DAG.getConstant(0, cast<AtomicSDNode>(Node)->getMemoryVT());
-  SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
-                               cast<AtomicSDNode>(Node)->getMemoryVT(),
+  SDValue Zero = DAG.getConstant(0, VT);
+  SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
                                Node->getOperand(0),
                                Node->getOperand(1), Zero, Zero,
                                cast<AtomicSDNode>(Node)->getMemOperand(),
@@ -10425,7 +10424,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
   }
   case ISD::ATOMIC_CMP_SWAP: {
     EVT T = N->getValueType(0);
-    assert (T == MVT::i64 || T == MVT::i128 && "can only expand cmpxchg pair");
+    assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
     bool Regs64bit = T == MVT::i128;
     EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
     SDValue cpInL, cpInH;